High-speed Logic Circuits Research Articles

Solution-processable ordered defect compound semiconductors for high-performance electronics.

Solution-processable semiconductors hold promise in enabling applications requiring cost-effective electronics at scale but suffer from low performance limited by defects. We show that ordered defect compound semiconductor CuIn5Se8, which forms regular defect complexes with defect-pair compensation, can simultaneously achieve high performance and solution processability. CuIn5Se8 transistors exhibit defect-tolerant, band-like transport supplying an output current above 35 microamperes per micrometer, with a large on/off ratio greater than 106, a small subthreshold swing of 189 ± 21 millivolts per decade, and a high field-effect mobility of 58 ± 10 square centimeters per volt per second, with excellent uniformity and stability, superior to devices built on its less defective parent compound CuInSe2, analogous binary compound In2Se3, and other solution-deposited semiconductors. They can be monolithically integrated with carbon nanotube transistors to form high-speed and low-voltage three-dimensional complementary logic circuits and with micro-light-emitting diodes to realize high-resolution displays.

Dynamical modes in a vertical nanocontact-based spin Hall nano-oscillator

Spin-torque nano-oscillators (STNOs) with high nonlinear tunability can serve as nanoscale spin-wave emitters for high-speed magnon-based logic circuits and neural networks for promising new energy-efficiency computing. Although various STNOs have been modeled theoretically and characterized experimentally, there is a sustained effort to improve their coherence and nonlinear tunability. By using numerical simulation, here we explore the evolution rule of spectral characteristics and nonlinearities of the emitted coherent spin waves in a type of spin Hall nano-oscillator (SHNO) with a perpendicular magnetic anisotropy (PMA) coefficient ${K}_{u}$, which is based on a vertical nanocontact fabricated on an extended heavy metal/ferromagnet bilayer. There exist three distinct dynamic regimes with varying ${K}_{u}$. At the easy-plane anisotropy-dominated in-plane magnetized regime, the SHNO exhibits coexistence of the nonlinear self-localized spin-wave bullet mode with a significantly negative nonlinearity coefficient $\ensuremath{\aleph}$ and a secondary high-frequency quasilinear edge mode at higher current density. The latter excitation is supported by the energy transfer from the former via nonlinear coupling rather than the injected spin currents located in the center nanogap of the device. When the easy-plane shape anisotropy is effectively compensated by PMA, only a single quasipropagating spin-wave mode with a near-zero $\ensuremath{\aleph}$ is excited at lower current density, consistent with minimization of nonlinear damping due to the suppression of nonlinear mode coupling. For the out-of-plane magnetized SHNOs with ${K}_{u}$ above the demagnetization energy, a well-defined propagating spin-wave mode with a positive $\ensuremath{\aleph}$, characterized by a significant frequency blueshift and a rightward elongated spatial profile perpendicular to the in-plane component of the applied magnetic field, is observed. This detailed evolution diagram of auto-oscillating dynamics on the PMA coefficient ${K}_{u}$ provides a practical approach to selectively excite dynamical modes and optimize the spectral characteristics of the SHNO for applications in microwave technology and spin-wave logic.

Correlation between the magnitude of interlayer exchange coupling and charge-to-spin conversion efficiency in a synthetic antiferromagnetic system

The correlation between the magnitude of interlayer exchange coupling (J ex) and charge-to-spin conversion efficiency (spin Hall angle: θ SH) is investigated in a synthetic antiferromagnetic (AF) system with compensated magnetization. The magnitude of θ SH increases linearly with increasing the magnitude of J ex. We observe the factor of 6.5 increase of spin Hall angle (θ SH = 45.8%) in a low resistive (ρ xx = 41 μΩcm) synthetic AF system by increasing the magnitude of J ex. The low resistive synthetic AF system will be a promising building block for future nonvolatile high-speed memories and logic circuits using the spin Hall effect.

Systematic Design of Loop Circuit Topologies Using C/I DS Methodology

Herein, a systematic approach for designing loop topology circuits, such as ring oscillators (ROs), latches, and frequency dividers, is proposed. The design flow is devised to implement the target circuits with minimum power dissipation at the desired operating frequency. Using a modified <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$C/I_{\text {DS}}$ </tex-math></inline-formula> methodology, several design examples in different technology nodes are provided showing less than ±5% error in the estimated circuit performance, confirmed by experimental data in 0.18 <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${\mu }\text{m}$ </tex-math></inline-formula> technology. A standardized procedure has been developed to extract fundamental device characteristics for different technology nodes, which are subsequently fed into an optimizer script. Examples for implementing current-steering ROs and frequency dividers will be provided. The proposed approach can be employed to custom design high-speed sequential logic circuits, as well as voltage-controlled oscillators (VCOs), digitally controlled oscillators (DCOs), and frequency dividers for applications such as clock generators, sequential circuits, and serial data transceivers in modern integrated systems.

Ultra-compact terahertz all-optical logic comparator on GaAs photonic crystal platform

Photonic crystals are suitable structures for designing various types of optical logic circuits. In this paper, an all-optical comparator is designed and simulated using two-dimensional photonic crystals. A combination of linear and point defects has been used in the proposed structure. The small number of point defects and the use of simple linear defects make this comparator simple design. One of the important features of this comparator is that it uses two outputs to compare the input bits. A small structure is used for the proposed optical comparator. Also, this structure has a delay time of 0.07 ps, which is due to the very small size of the structure and the use of a small number of defects. The simulation results show that the bit rate for the proposed comparator is 3.33 Tb/s. Therefore, this structure can be suitable for use in high-speed logic circuits.

DEVICE AND CIRCUIT LEVEL SIMULATION STUDY OF NOR GATE LOGIC FAMILIES DESIGNED USING NANO-MOSFETs

The investigation of silicon-based nano-MOSFETs logic circuits is helpful to gain more comprehensive knowledge about nanoscale transistors. Therefore, a simulation study has been performed on four logic families of two inputs NOR gate logic circuits, namely (i) nano-CMOS NOR gate, (ii) nano-MOSFET loaded n-type nano-MOSFET NOR gate, (iii) 733.8 Ω resistive loaded nano-MOSFET NOR gate, and finally (iv) pseudo-n-type nano-MOSFET NOR gate. The nano-MOSFET technology node studied in this paper is 10 nm. Device simulation is done using an online NanoMOS simulator, whereas circuit simulation is carried out using freeware WinSpice. The main obstacle encountered during downscaling of nano-MOSFETs is low power dissipation and high-speed nano-MOSFET logic circuits. Correct logical NOR operation has been proven by observing simulated timing waveforms. Transient timing analysis on nano-MOSFET loaded n-type nano-MOSFET NOR gate has shown that propagation delays calculated from theory and simulation are 66% matched. From the analysis, this 10 nm nano-MOSFET NOR logic circuit design exhibit a dynamic power reduction of 148 times and a propagation delay improvement of 33 times when benchmarked against a typical 120 nm MOSFET logic circuit.&#x0D; Keywords: nano transistor, electrical characteristics, channel length, channel width, benchmarking, power, speed

Cross-Layer Dual Modular Redundancy Hardened Scheme of Flip-Flop Design Based on Sense-Amplifier

As the demand for low-power and high-speed logic circuits increases, the design of differential flip-flops based on sense-amplifier (SAFF), which have excellent power and speed characteristics, has become more and more popular. Conventional SAFF (Con SAFF) and improved SAFF designs focus more on the improvement of speed and power consumption, but ignore their Single-Event-Upset (SEU) sensitivity. In fact, SAFF is more susceptible to particle impacts due to the small voltage swing required for differential input in the master stage. Based on the SEU vulnerability of SAFF, this paper proposes a novel scheme, namely cross-layer Dual Modular Redundancy (DMR), to improve the robustness of SAFF. That is, unit-level DMR technology is performed in the master stage, while transistor-level stacking technology is used in the slave stage. This scheme can be applied to some current typical SAFF designs, such as Con SAFF, Strollo SAFF, Ahmadi SAFF, Jeong SAFF, etc. Detailed HSPICE simulation results demonstrate that hardened SAFF designs can not only fully tolerate the Single Node Upset of sensitive nodes, but also partially tolerate the Double Node Upset caused by charge sharing. Besides, compared with the conventional DMR hardened scheme, the proposed cross-layer DMR hardened scheme not only has the same fault-tolerant characteristics, but also greatly reduces the delay, area and power consumption.

Design of High-Speed Logic Circuits with Four-Step RRAM-Based Logic Gates

The RRAM (resistive random-access memory) is one of the most competitive candidates of the emerging non-volatile memory devices. In recent years, the RRAM has been used as memory device and also to build logic circuit. However, the design method of the RRAM-based logic circuit is still an open issue. This paper proposes a design method of logic circuit based on the four-step RRAM logic gates. The design rules are studied for both the combinational and the sequential logic circuits in a parallel style. The design practices and synthesis results show that the proposed methods generate the high-performance circuits for the arbitrary logic functions. Moreover, the four-step RRAM-based logic gates are suitable for designing the circuits with pipelined architecture, since the different RRAM logic blocks have the uniform working speed. The pipelined N-bit ripple carry adder and the N-bit multiplier outperform the other RRAM base counterparts; the output results are obtained only with 2N + 2 and 6N− 4 working cycles, respectively.

A New Technique for Designing Low-Power High-Speed Domino Logic Circuits in FinFET Technology

In this paper, a fin field-effect transistor (FinFET)-based domino technique dynamic node-driven feedback transistor domino logic (DNDFTDL) is designed for low-power, high-speed and improved noise performance. In the proposed domino technique, the concept of current division is explored below the evaluation network for enhancement of performance parameters. Simulations are carried out for 32-nm complementary metal–oxide–semiconductor (CMOS) and FinFET node using HSPICE for 2-, 4-, 8- and 16-input OR gates with a DC supply voltage of 0.9[Formula: see text]V. Proposed technique shows a maximum power reduction of 73.93% in FinFET short-gate (SG) mode as compared to conditional stacked keeper domino logic (CSKDL) technique and a maximum power reduction of 72.12% as compared to modified high-speed clocked delay domino logic (M-HSCD) technique in FinFET low-power (LP) mode. The proposed technique shows a maximum delay reduction of 35.52% as compared to voltage comparison domino (VCD) technique in SG mode and a reduction of 25.01% as compared to current mirror footed domino logic (CMFD) technique in LP mode. The unity noise gain (UNG) of the proposed circuit is 1.72–[Formula: see text] higher compared to different existing techniques in FinFET SG mode and is 1.42–[Formula: see text] higher in FinFET LP mode. The Figure of Merit (FOM) of the proposed circuit is up to [Formula: see text] higher as compared to existing domino logic techniques because of lower values of power, delay and area and higher values of UNG of the proposed circuit. In addition, the proposed technique shows a maximum power reduction of up to 68.64% in FinFET technology as compared to its counterpart in CMOS technology.

(Invited) High-Performance 2D Tellurium Transistors Towards CMOS Logic Applications

The thirst for novel two-dimensional (2D) materials for ultra-scaled electronics keeps growing during the last decade as the downsizing trend of silicon-based conventional semiconductors is approaching its physical limit. An ideal paradigm of 2D materials suitable for logic device applications should possess high carrier mobility for both type of carriers, good air-stability, controllable doping scheme and a reasonable bandgap. Recently reported hydrothermal growth technique of 2D tellurium (Te) thin films, which meet all the above criteria, offers a new option for 2D material-based CMOS applications. Tellurium is a narrow bandgap p-type semiconductor (0.35 eV) with nearly symmetric mobilities for both electrons and holes of around 700 cm2/Vs at room temperature. It has one-dimensional chiral crystal structure and can be grown into 2D films under right conditions. Just like other 2D materials, these 2D facets of Te also contain no dangling bonds and therefore the 2D films can preserve the material properties and have great potential for miniaturizing device geometry in principle. Here we first report systematic investigation of 2D Te p-type transistor performance approaching atomic-thin limit. The device key parameters, such as field-effect mobility, on/off ratio and stability were thoroughly studied as a function of film thickness. The device performance was then optimized through contact and dielectric engineering, and large drive current over 1 A/mm was achieved. We further employed photo-current mapping method to show that rare accumulation-type ohmic contacts were formed using high work function metal (palladium). Finally, we present an atomic layer deposited (ALD) dielectric doping technique to effectively dope the intrinsically p-type channel into n-type with almost symmetric operations for both NMOS and PMOS. Prototypical inverters based on Te CMOS demonstrate great potential of constructing Te-based high-speed CMOS logic circuits. Our work not only established a comprehensive guideline for designing and optimizing 2D Te based CMOS devices, but also provided a device platform to explore versatility of 2D Te from many other perspectives, such as condensed matter physics and thermoelectronics.

The N3XT Approach to Energy-Efficient Abundant-Data Computing

The world’s appetite for analyzing massive amounts of structured and unstructured data has grown dramatically. The computational demands of these abundant-data applications, such as deep learning, far exceed the capabilities of today’s computing systems and are unlikely to be met with isolated improvements in transistor or memory technologies, or integrated circuit architectures alone. To achieve unprecedented functionality, speed, and energy efficiency, one must create transformative nanosystems whose architectures are based on the salient properties of the underlying nanotechnologies. Our Nano-Engineered Computing Systems Technology (N3XT) approach makes such nanosystems possible through new computing system architectures leveraging emerging device (logic and memory) nanotechnologies and their dense 3-D integration with fine-grained connectivity to immerse computing in memory and new logic devices (such as carbon nanotube field-effect transistors for implementing high-speed and low-energy logic circuits) as well as high-density nonvolatile memory (such as resistive memory), and amenable to ultradense (monolithic) 3-D integration of thin layers of logic and memory devices that are fabricated at low temperature. In addition, we explore the use of several device and integration technologies in the N3XT beyond the specific ones mentioned earlier that are also used in our main nanosystem prototypes. We also present an efficient resiliency technique to overcome endurance challenges in certain resistive memory technologies. N3XT hardware prototypes demonstrate the practicality of our architectures. We evaluate the benefits of the N3XT using a simulation framework calibrated using experimental measurements. System-level energy-delay product of common implementations of abundant-data workloads improves by three orders of magnitude in the N3XT compared with conventional architectures. These improvements impact a broad range of application workloads and architecture configurations, from embedded systems to the cloud.

Physical Simulations of High Speed and Low Power NanoMagnet Logic Circuits

Among all “beyond CMOS” solutions currently under investigation, nanomagnetic logic (NML) technology is considered to be one of the most promising. In this technology, nanoscale magnets are rectangularly shaped and are characterized by the intrinsic capability of enabling logic and memory functions in the same device. The design of logic architectures is accomplished by the use of a clocking mechanism that is needed to properly propagate information. Previous works demonstrated that the magneto-elastic effect can be exploited to implement the clocking mechanism by altering the magnetization of magnets. With this paper, we present a novel clocking mechanism enabling the independent control of each single nanodevice exploiting the magneto-elastic effect and enabling high-speed NML circuits. We prove the effectiveness of this approach by performing several micromagnetic simulations. We characterized a chain of nanomagnets in different conditions (e.g., different distance among cells, different electrical fields, and different magnet geometries). This solution improves NML, the reliability of circuits, the fabrication process, and the operating frequency of circuits while keeping the energy consumption at an extremely low level.

A Two-Way Interleaved 7-b 2.4-GS/s 1-Then-2 b/Cycle SAR ADC With Background Offset Calibration

This paper presents a 2 $\times $ time-interleaved 7-b 2.4-GS/s 1-then-2 b/cycle SAR ADC in 28-nm CMOS. The process-voltage-temperature sensitivity of a multi-bit SAR architecture has been improved by the proposed 1-then-2 b/cycle scheme with background offset calibration. With the pre-charge reduction scheme, the traditional large switching energy and time consuming pre-charge operation have been removed, which simultaneously enables a simple control logic without the need of a ${V}_{\mathrm{ cm}}$ voltage. Besides, a background offset calibration is implemented on chip which does not involve any extra phase or calibration input signal. Its operation is well embedded within the 1-then-2 b/cycle architecture, thus leading to a very minimal modification of the ADC core. With an improved fringing DAC structure and a high-speed dynamic logic circuit, a single-channel ADC can work at 1.2 GS/s under a 0.9-V supply. Using two-way time interleaving, the prototype samples at 2.4 GHz and consumes 5-mW power including the on-chip background offset calibration. It exhibits a 40.05-dB SNDR at Nyquist, leading to a Walden FoM of 25.3 fJ/conversion step. Measurement results show that the SNDR of the ADC can be kept above 38 dB at 2 GS/s under a wide range of temperature, supply, and input common-mode variation.

High-Quality Reconfigurable Black Phosphorus p-n Junctions

The p-n junction is the fundamental building block for electronics and photonics applications. In a conventional p-n junction, the performance parameters cannot be tuned due to the fixed doping level after ion implantation. In this paper, reconfigurable p-n or n-p junctions were built based on the ambipolar black phosphorus (BP) and other 2-D materials, namely, graphene and hexagonal boron nitride (h-BN). High-quality graphene/h-BN/BP/h-BN sandwich device was created by the dry transfer method in an inert environment. Graphene serves as the local back gate, which can tune BP partially into either n-type or p-type material. The rest of the BP channel can be controlled by the back gate. The BP encapsulated device can enable the high performance of the ideality factor down to 1.08 (p-n junction) and 1.18 (n-p junction). The device developed in this paper has a more balanced ideality factor than previously reported reconfigurable WSe2 and BP devices. By tuning the back gate and graphene gate, the BP device can be tuned into four operational quadrants, namely, n-n, n-p, p-n, and p-p junctions. Moreover, the hole mobility of BP is up to 404 cm2/ $\text {V}\cdot \text {s}$ at room temperature. Our work shows that the BP heterostructure is very promising for high-speed reconfigurable logic functions and circuits.

Ferroelectric Gate AlGaN/GaN E-Mode HEMTs With High Transport and Sub-Threshold Performance

This letter demonstrated AlGaN/GaN enhancement-mode (E-mode) high-electron-mobility transistors (HEMTs) with 30-nm Pb(Zr,Ti)O3 ferroelectric gate dielectric. The high-quality interface and polarization coupling resulted in the initial pre-poled ferroelectric polarization toward surface. Then, ferroelectric polarization engineering and gate poling were studied, realizing E-mode HEMTs with very high field-effect mobility of 1819 cm2/ $\text{V}\cdot \text{s}$ , ON/OFF current ratio larger than $10^{10}$ , and the low sub-threshold slope of 90 mV/decade. Owing to the undestroyed 2-D electron gases channel, ferroelectric gate GaN-based E-mode HEMTs with high transport performance are promising candidates for high-speed logic circuit applications.

All-optical comparator using logic operations based on nonlinear properties of semiconductor optical amplifier

High-speed all-optical logic circuits have attracted much attention because of their important roles in signal processing in next-generation optical networks. We demonstrate an all-optical two bit comparator using an optical gate architecture based on semiconductor optical amplifiers. The scheme, able to process input signals at the same or different wavelengths, is characterized using return-to-zero modulated signals at 10 Gb/s. Clear open eye patterns and correct logic bit sequences with extinction ratios exceeding 9 dB are achieved. Potential for integration and simple structure makes this architecture an interesting approach in optical signal processing and photonic computing.

Monolithic Integration of InAs Quantum-Well n-MOSFETs and Ultrathin Body Ge p-MOSFETs on a Si Substrate

Integration of In x Ga1– x As n-MOSFETs and Si y Ge1– y p-MOSFETs could be a key to realize future low-power and high-speed logic circuits. In this paper, monolithic integration of InAs n-MOSFETs and Ge p-MOSFETs on a Si substrate is reported. To address the challenge of integrating materials with large lattice mismatch (InAs and Ge on Si substrate), a sub-120-nm GaSb-on-GaAs buffer on a germanium-on-insulator (GeOI) starting substrate is employed. The strain resulting from the 7.78% lattice mismatch between the GaSb and GaAs layers is mainly relaxed via interfacial misfits at the GaSb/GaAs interface, enabling significant reduction in the buffer thickness. For device fabrication, a self-aligned gate last process flow with Si-CMOS-compatible modules is used. To realize raised source-drain device architecture, a combination of dry and digital etch processes is developed to etch InAs and Ge cap layers. Devices with channel thicknesses less than 5 nm and channel lengths less than 200 nm are realized for both n- and p-MOSFETs, with promising electrical characteristics.

Single-Event Performance of Sense-Amplifier Based Flip-Flop Design in a 16-nm Bulk FinFET CMOS Process

The increasing need for high-speed logic circuits is causing the conventional flip-flop (FF) designs to migrate to differential FF designs. With the small magnitude of input voltages (and the resulting small noise margins) needed for proper operation, sense-amplifier based FF designs (SAFF) are susceptible to single-event effects (SEE). Single event upset (SEU) performance of high-speed SAFF designs is investigated in this paper for 16-nm bulk FinFET CMOS technology. SEU cross-sections for SAFF are evaluated over particle LET, temperature, and operating frequency. Results show significant increases in cross-sections as a function of frequency, but not so for temperature. Results presented in this work can guide designers to harden the SAFF that satisfies their specific circuit SEU error rate constraints.

Comparing and Combining Measurement-Based and Driven-Dissipative Entanglement Stabilization

We demonstrate and contrast two approaches to the stabilization of qubit entanglement by feedback. Our demonstration is built on a feedback platform consisting of two superconducting qubits coupled to a cavity which are measured by a nearly-quantum-limited measurement chain and controlled by high-speed classical logic circuits. This platform is used to stabilize entanglement by two nominally distinct schemes: a "passive" reservoir engineering method and an "active" correction based on conditional parity measurements. In view of the instrumental roles that these two feedback paradigms play in quantum error-correction and quantum control, we directly compare them on the same experimental setup. Further, we show that a second layer of feedback can be added to each of these schemes, which heralds the presence of a high-fidelity entangled state in realtime. This "nested" feedback brings about a marked entanglement fidelity improvement without sacrificing success probability.

Market-Based Values [Market-Based Analyses

I lost before the conversation really began. Art opened our discussions with a sharp and pointed question. ?Why did you start on consumer engineering with radio engineers? The telephone was the first consumer electrical product.? Art is an old-school electrical engineer. He is equally comfortable with a motor controller, a power substantiation, or a high-speed logic circuit. In the past, he has tolerated my claims that all engineering is now a form of software engineering, but this time he clearly felt that I missed some fundamental lessons about how engineers interact with the public.