High-speed Image Acquisition System Research Articles

High-speed image acquisition system and FPGA implementation

To solve the problem of low speed and poor quality of image acquisition, a system of high-speed image acquisition based on NiosⅡ was introduced. First of all, Field-Programmable Gate Array (FPGA) was used for controlling image sensor, and the image was captured through ping-pang operation. Then, the principle of area exchange rate was used for image processing. After that, the data was kept and transmitted to the upper device by image compression algorithm of BP neural network. Through the simulation experiments from the acquired data, the simulation results demonstrate that this system provides image acquisition of higher speed and quality than traditional system.

The Design of High-Speed CMOS Imaging System Based on SOPC Technology

This paper introduces a design of a high-speed image acquisition system based on Avalon bus which is supported with SOPC technology. Some peripherals embedded in Avalon bus were customized and utilized in this system, such as imaging unit, decoding unit and storage unit, and these improved the speed of the whole imaging system. The data is compressed to three-fourths of the original by the decoding unit. A custom DMA is designed for moving the image data to the two caches of the SDRAM. This approach discards the method that FIFO must be put up in the traditional data acquisition system. And therefore, it reduced the CPU’s task for data moving. At the same time, the image acquisition and the data transmission can complete a parallel job. Finally, the design is worked on the high-speed image acquisition system which is made up of 2K*2K CMOS image sensor. And it improved the image acquisition speed by three ways: data encoding, custom DMA controller and the parallel processing.

A 10 000 fps CMOS Sensor With Massively Parallel Image Processing

A high-speed analog VLSI image acquisition and pre-processing system has been designed and fabricated in a 0.35 ¿m standard CMOS process. The chip features a massively parallel architecture enabling the computation of programmable low-level image processing in each pixel. Extraction of spatial gradients and convolutions such as Sobel or Laplacian filters are implemented on the circuit. For this purpose, each 35 ¿m × 35 ¿m pixel includes a photodiode, an amplifier, two storage capacitors, and an analog arithmetic unit based on a four-quadrant multiplier architecture. The retina provides address-event coded output on three asynchronous buses: one output dedicated to the gradient and the other two to the pixel values. A 64 × 64 pixel proof-of-concept chip was fabricated. A dedicated embedded platform including FPGA and ADCs has also been designed to evaluate the vision chip. Measured results show that the proposed sensor successfully captures raw images up to 10 000 frames per second and runs low-level image processing at a frame rate of 2000 to 5000 frames per second.

An SIMD Programmable Vision Chip with High-Speed Focal Plane Image Processing

AbstractA high-speed analog VLSI image acquisition and low-level image processing system are presented. The architecture of the chip is based on a dynamically reconfigurable SIMD processor array. The chip features a massively parallel architecture enabling the computation of programmable mask-based image processing in each pixel. Extraction of spatial gradients and convolutions such as Sobel operators are implemented on the circuit. Each pixel includes a photodiode, an amplifier, two storage capacitors, and an analog arithmetic unit based on a four-quadrant multiplier architecture. A "Equation missing" pixel proof-of-concept chip was fabricated in a 0.35 "Equation missing"m standard CMOS process, with a pixel size of 35 "Equation missing"m "Equation missing" 35 "Equation missing"m. A dedicated embedded platform including FPGA and ADCs has also been designed to evaluate the vision chip. The chip can capture raw images up to 10 000 frames per second and runs low-level image processing at a framerate of 2 000 to 5 000 frames per second.

Experimental wetting dynamics study of eutectic and lead-free solders with various fluxes, isothermal conditions, and bond pad metallizations

Demands on solder bump interconnects have increased in modern electronics. This is characterized by high density, small size, and fine-pitch devices. In solder bump interconnects, solder wetting onto bond pads is the key factor that determines the interconnect process yield and the solder joint reliability. Solder wetting involves various physical phenomena such as surface tension imbalance, viscous dissipation, molecular kinetic motion, chemical reaction, and diffusion. In this paper, an experimental study on solder wetting dynamics will be presented. The effects of solder reflow process parameters and bonding materials will be discussed, as they relate to the physics of solder wetting and ultimately the interconnect process yield and solder joint reliability. The experimental setup consists of a high-speed image acquisition system and a temperature chamber which were used to measure the time dependent behavior of molten solder spheres onto bond pads under an isothermal condition. The solder materials investigated were eutectic tin-lead solder and lead-free 95.5Sn-4.0Ag-0.5Cu solder. The wetting dynamics of the solder materials were investigated on pure Cu bond pads and Cu/Ni/Au bond pads, with several different flux systems, at different environmental temperatures and with various solder sphere sizes. The experimental observations indicate that the wetting dynamics clearly depend on temperature, solder materials, and substrate metallization but do not depend significantly on the flux system or the solder sphere size.

A high-speed image acquisition system for robotics

There are many applications in industry for imaging systems. The majority of these use a video camera as the input device. The output from the camera is sampled and stored in memory and a computer used to analyse the image. Until recently, the time for the analysis of the image was relatively long in comparison with the acquisition time of the image. However, with the development of new high-speed microprocessors decreasing the processing time, the acquisition time of the image will become the limiting factor of the analysis rate. This paper describes the development of a prototype system to make possible the capture of a full frame image (256 lines), in under 15 ms, for analysis by a computer. With the use of programmable logic devices (PLDS) and hardware windowing techniques, the acquisition time for a part frame (40 lines) is 2.8 ms. Shorter acquisition times can be obtained, but with reduned resolution. An application of the imaging system is also presented.