Digital High Speed Research Articles

Development of a digital amplifier system for cut-open oocyte electrophysiology

The cut-open oocyte Vaseline gap technique is a powerful electrophysiological method for the characterization of ion channels. However, traditional amplifiers for cut-open oocyte Vaseline gap are labor intensive and require significant user expertise. We introduce an innovative, open-source digital amplifier system with high-speed digitization and software-controlled electronics for computer-driven automation. This system compares well to existing commercial systems in terms of conventional specifications of step response (current peak at 25μs and decay of 36μs time constant), current noise (1.0 nA at 3-kHz bandwidth), and dynamic range (96.9 dB). Additionally, it unlocks new methods through close integration of the amplifier and software, including machine-learning techniques for tuning capacitive compensation waveforms, achieving a 100-fold suppression of mean-squared transient current, and impedance measurement methods to identify system components such as membrane capacitance and electrode resistances. For future extensions, the design has unique attributes such as real-time digital signal processing for feedback, multiple input and multiple output, and allows for user customization. By providing open-source access to the circuit board designs, control software, and field-programmable gate array code on GitHub, this approach aims to foster cross-disciplinary collaboration and facilitate instrument customization enabling previously inaccessible electrophysiology experiments.

Development of [formula omitted]/[formula omitted]/[formula omitted] discrimination with the phoswich detector using improved charge comparison method

Both pulse shape discrimination methods based on temporal difference characteristic and phoswich detectors are well-known and effective for particles discrimination, so the combination and further improvement are significant for better performance. In this paper, a phoswich detector combining YAG(Ce) and CsI(Tl) was constructed for α/β/γ discrimination using various techniques including two machine learning algorithms and an improved charge comparison method that further exploited the difference in the decay rate of pulse tail. The detector was designed with Geant4, simulating the suitable sizes of scintillators, and a high-speed digitizer was used for the collection of pulses that were from three radioactive sources. The results among the α (β) and γ rays had the figure of merit values greater than 2, simultaneously with an optimal 1.68 of the improved method that had more than twice the performance comparing the original 0.69 for α/β identification, which showed the detector is able to discriminate α, β and γ rays in mixed radiation field effectively.

Development of a toroidally resolved broadband ECE imaging system for measurement of turbulent fluctuations on the KSTAR.

The two electron cyclotron emission imaging (ECEI) systems installed at adjacent ports (G and H) on the KSTAR tokamak incorporate large-aperture mm-wave optics, broadband electronics, and high speed digitization (up to 1 MSa/s) for 2D and quasi-3D visualization of MHD-scale fluid dynamics. Recently, the ECEI systems have been proved to be capable of visualization of smaller scale fluctuations albeit with a limited spatiotemporal resolution and even capable of measurement of ion cyclotron harmonic waves by direct high-speed sampling of the ECE IF signals. A four-channel prototype subsystem with a higher sampling rate up to 16 GS/s has been integrated into the G-port ECEI system, enabling the measurement of plasma waves in the GHz range in the form of modulated ECE signals and characterization of high-frequency turbulence during the evolution of pedestal. To achieve higher toroidal resolution in the turbulence measurement, the H-port ECEI system is now being upgraded to have a toroidally dual detector array of 2(toroidal) × 12(vertical) × 8(radial) channel configuration and a high-speed subsystem of 2(toroidal) × 4 channel configuration. The new mm-wave optics has been designed via beam propagation simulation, and the measured performance of the fabricated lens indicates a toroidal resolution of 8-10cm depending on the focus position and zoom factor, allowing for the measurement of parallel wavenumber up to k‖ ∼ 0.8cm-1.

Advancing precision in pipeline analog-to-digital converters: Leveraging MATLAB for design and analysis in next-generation communication systems

The integration of MATLAB in designing and analyzing pipeline Analog-to-Digital Converters (ADCs) addresses the complexities of next-generation communication systems. This study reviews literature to identify trends and challenges in high-speed ADC designs. Mastery of MATLAB and its toolboxes, like Simulink and Signal Processing, is essential for advanced ADC modeling and analysis. Key challenges include maintaining accuracy with diminishing supply voltages in modern semiconductors. The study explores incorporating high-voltage analog components and develops strategies for superior accuracy using low-voltage transistors. MATLAB and pipeline architecture are crucial for advancing ADC design, providing innovative solutions for next-gen communication systems.

The influence of phase noise and nonlinear distortions of high-speed digital-to-analog converters on the parameters of digital communication systems

Problem statement. The trend in modern microwave electronics to transfer analog functions to the digital domain has led to the emergence and active use of high-speed digital-to-analog converters (DACs) in special operating modes in promising communication systems. However, optimization of power consumption and economic costs of signal generators (for example, through the use of simplified clock generators or by saving FPGA memory) leads to an increase in phase noise and nonlinear distortions in the output signal, which has a significant impact on the parameters of the communication system. Goal. Evaluation of phase noise and nonlinear distortions of signal generators based on high-speed digital-to-analog converters, as well as the study of their effect on the parameters of a digital communication system. Results. Expressions for estimating the spectral power density of phase noise of a signal generator based on a high-speed DAC are proposed. It is determined that the level of phase noise of the shaper is mainly determined by the noise of the clock generator. The jitter of the communication system was evaluated when using a surfactant generator and a PLL-based synthesizer as a clock generator. A mathematical model of the output signal of the shaper is proposed, taking into account nonlinear distortions caused by sampling, phase code truncation and amplitude quantization. A model of a communication system with multi-position quadrature amplitude modulation has been developed to evaluate parameters taking into account phase noise and nonlinear distortion of the shaper based on high-speed DACs. It is determined that the intrinsic phase noise of the signal generator leads to an increase in the probability of bit error (by about an order of magnitude compared to ideal formers). The use of surfactant generators as clock generators makes it possible to reduce the probability of bit errors of the communication system by 3-5 times compared with PLL-based synthesizers. Practical significance. It is shown that the displacement of points in the signal constellation is mainly influenced by nonlinear distortions of the output signal of high-speed DACs caused by truncation of the phase code, as well as incomplete suppression of spectral components located in the neighboring Nyquist zone. The proposed mathematical apparatus makes it possible to determine the optimal frequency ratios in the structure of the shaper, at which the lowest values of the displacement of the constellation points are achieved.

Sensitive Discrete Frequency Mid-Infrared Absorption Spectroscopy Using Digitally Referenced Detection.

Broadly tunable mid-infrared (IR) lasers, including quantum cascade lasers (QCL), are an asset for vibrational spectroscopy wherein high-intensity, coherent illumination can target specific spectral bands for rapid, direct chemical detection with microscopic localization. These emerging spectrometers are capable of high measurement throughputs with large detector signals from the high-intensity lasers and fast detection speeds as short as a single laser pulse, challenging the decades old benchmarks of Fourier transform infrared spectroscopy. However, noise in QCL emissions limits the feasible acquisition time for high signal-to-noise ratio (SNR) data. Here, we present an implementation that is broadly compatible with many laser-based spectrometer and microscope designs to address these limitations by leveraging high-speed digitizers and dual detectors to digitally reference each pulse individually. Digitally referenced detection (DRD) is shown to improve measurement sensitivity, with broad spectral indifference, regardless of imbalance due to dissimilarities among system designs or component manufacturers. We incorporated DRD into existing instruments and demonstrated its generalizability: a spectrometer with a 10-fold reduction in spectral noise, a microscope with reduced pixel dwell times to as low as 1 pulse while maintaining SNR normally achieved when operating 8-fold slower, and finally, a spectrometer to measure vibrational circular dichroism (VCD) with a ∼ 4-fold reduction in scan times. The approach not only proves versatile and effective but can also be tailored for specific applications with minimal hardware changes, positioning it as a simple and promising module for spectrometer designs using lasers.

Performance of JT-60SA Thomson Scattering data analysis system

We have developed signal processing routines for the Thomson Scattering measurement, which is planned for use in the next campaign of the JT-60SA large-scale tokamak experiment.This paper provides the data analysis system and its performance evaluated in terms of computation time and error.The sequential routine of determining the scattered light intensity from a simulated signal, including noise data from a 1 Gs/s high-speed sampling digitizer, and determining the electron temperature and density was tested for the first time on an actual machine.The data analysis system ensures that electron temperature and density can be calculated with reasonable relative errors and within a realistic time frame for operations on JT-60SA.

A 12bit 1.6 GS/s pipelined ADC with multi-level dither injection achieving 68 dB SFDR over PVT

This paper presents a 12-bit 1.6 GS/s pipelined analog-to-digital converter (ADC) in a 40-nm CMOS process. A novel dual-capacitor dither injection technique was proposed, based on a randomize multi-level uniform logic, aimed at leveraging multi-level signal jitter to disperse higher-order harmonics and spurious signals within the spectrum. The technique proves highly effective in preserving the linearity of high-speed pipeline ADCs under Process, Voltage, and Temperature (PVT) variations. Additionally, a high-speed amplifier with SC net was designed, and its matching bias circuit design can achieve configurable performance adjustment according to circumstances. Measurement results show that the ADC attains an impressive Signal-to-Noise and Distortion Ratio (SNDR) of 55.9 dB and Spurious-Free Dynamic Range (SFDR) of 71.7 dB at the Nyquist frequency. Furthermore, the SFDR variation remains below 4.2 dB over the temperature range of −40 °C–85 °C.

2-Photon imaging of fluorescent proteins in living swine

A common point of failure in translation of preclinical neurological research to successful clinical trials comes in the giant leap from rodent models to humans. Non-human primates are phylogenetically close to humans, but cost and ethical considerations prohibit their widespread usage in preclinical trials. Swine have large, gyrencencephalic brains, which are biofidelic to human brains. Their classification as livestock makes them a readily accessible model organism. However, their size has precluded experiments involving intravital imaging with cellular resolution. Here, we present a suite of techniques and tools for in vivo imaging of porcine brains with subcellular resolution. Specifically, we describe surgical techniques for implanting a synthetic, flexible, transparent dural window for chronic optical access to the neocortex. We detail optimized parameters and methods for injecting adeno-associated virus vectors through the cranial imaging window to express fluorescent proteins. We introduce a large-animal 2-photon microscope that was constructed with off-the shelf components, has a gantry design capable of accommodating animals > 80 kg, and is equipped with a high-speed digitizer for digital fluorescence lifetime imaging. Finally, we delineate strategies developed to mitigate the substantial motion artifact that complicates high resolution imaging in large animals, including heartbeat-triggered high-speed image stack acquisition. The effectiveness of this approach is demonstrated in sample images acquired from pigs transduced with the chloride-sensitive fluorescent protein SuperClomeleon.

A Novel Framework of Genetic Algorithm and Spectre to Optimize Delay and Power Consumption in Designing Dynamic Comparators

In integrated circuit (IC) design, analog circuits contribute significantly as the interface between real and digital world signals. Although they make up a relatively small portion of the overall circuit, their design process is often most time-consuming, mostly from the phase of manual iteration of circuit parameters to meet design specifications. Therefore, the design automation of analog circuits with the help of efficient optimization techniques arises as a promising candidate to address the issue. Among optimization algorithms, while the genetic algorithm (GA) has been shown to be effective in finding near-optimal solutions, it has not been extensively applied to the field of analog circuit design. Hence, this paper proposes a method to utilize GA in the optimization of a widely used circuit topology, namely the comparator. The comparator is considered the fundamental block in the design of most analog-to-digital converters (ADCs). For high-speed ADCs, dynamic comparators are usually chosen for the purpose of high speed and power efficiency. In summary, this paper introduces an innovative GA-Spectre architecture to optimize the dynamic comparator with respect to delay and power consumption. The post-optimized results are optimistic with a 72.61 ps delay and 3.11 µW power dissipation.

Three-dimensional (3D) moment imaging with a USB3 oscilloscope.

We report a new implementation of a recently developed 3D momentum imaging technique [Lee etal. J. Chem. Phys. 141, 221101 (2014)]. The previously employed high-speed digitizer in the setup is replaced by a portable USB3 oscilloscope. A new triggering scheme was developed to suppress trigger jitters and to synchronize the signals from a camera and the oscilloscope. The performance of the setup was characterized in the study of laser desorption/ionization of 2,5-dihydroxybenzoic acid on a velocity map imaging apparatus. A ∼60 picosecond time resolution in measuring time-of-flight is achieved with a count rate of ∼1kHz, which is comparable to the system using high-speed digitizers. The new setup affords great portability and wider accessibility to the high-performing 3D momentum imaging technique.

PulseDL-II: A System-on-Chip Neural Network Accelerator for Timing and Energy Extraction of Nuclear Detector Signals

Front-end electronics equipped with high-speed digitizers are being used and proposed for future nuclear detectors. Recent literature reveals that deep learning models, especially one-dimensional convolutional neural networks, are promising when dealing with digital signals from nuclear detectors. Simulations and experiments demonstrate the satisfactory accuracy and additional benefits of neural networks in this area. However, specific hardware accelerating such models for online operations still needs to be studied. In this work, we introduce <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">PulseDL-II</i> , a system-on-chip (SoC) specially designed for applications of event feature (time, energy, etc.) extraction from pulses with deep learning. Based on the previous version, <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">PulseDL-II</i> incorporates a RISC CPU into the system structure for better functional flexibility and integrity. The neural network accelerator in the SoC adopts a three-level (arithmetic unit, processing element, neural network) hierarchical architecture and facilitates parameter optimization of the digital design. Furthermore, we devise a quantization scheme compatible with deep learning frameworks (e.g., TensorFlow) within a selected subset of layer types. We validate the correct operations of <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">PulseDL-II</i> on field programmable gate arrays (FPGA) alone and with an experimental setup comprising a direct digital synthesis (DDS) and analog-to-digital converters (ADC). The proposed system achieved 60 ps time resolution and 0.40% energy resolution at signal to noise ratio (SNR) of 47.4 dB.

Does the Opening of High-Speed Railway Promote Corporate Digital Transformation?

As China’s economy enters the digital era, guiding enterprises to conduct better digital transformations has become an urgent problem to be solved. In this regard, this paper builds a multiperiod DID model to empirically examine the impact of opening a high-speed railway (HSR) on corporate digital transformation by matching the data of HSR with the data of Shanghai and Shenzhen A-share listed companies from 2008 to 2019. It was found that (1) the opening of an HSR can significantly improve corporate digital transformation, and this finding still held after considering endogeneity issues and various robustness tests. (2) A heterogeneity analysis showed that the promoting effect of opening an HSR on corporate digital transformation was mainly found in nonstate enterprises, high-tech enterprises, and enterprises located in cities with low initial transportation endowment. (3) A mechanistic analysis found that opening an HSR can promote corporate digital transformation by promoting senior staff mobility, increasing industry competition, and enhancing financial agglomeration. This paper not only enriches the research related to the economic consequences of opening an HSR, but it also has important implications for guiding enterprises to successfully conduct corporate digital transformations.

A Real-Time Data Acquisition System for Single-Band Bathymetric LiDAR

Bathymetric light detection and ranging (LiDAR), which uses a laser with narrow pulse width and a high-repetition-rate, requires a real-time data acquisition system (RTDAQS) for quickly transmitting data with the characteristic of high sampling rates, high resolution and high accuracy. However, none of the RTDAQS in the world has reached these requirements. For this reason, this paper presents a RTDAQS with high speed SerDes data transfer technology based on the architecture of ADC+FPGA+ZYNQ. This RTDAQS consists of acquisition board and storage board. The acquisition board integrates high-speed analog-to-digital converter (ADC) acquisition module, Input/Output (I/O) control module, data transmission module, and Field Programmable Gate Array (FPGA) chip module. The storage board integrates FPGA Mezzanine Card (FMC) interface, solid state and ZYNQ chips. The corresponding software includes configuration for high-speed ADC acquisition module, I/O control module, data transmission module, and FMC interface module. The RTDAQS, which is embedded in the LiDAR with laser pulses width of 2.5ns ± 0.2ns and frequency of 500 Hz, has been verified by the experiments in indoor sink, outdoor pond, river, reservoir, Beihai Bay of the Pacific Ocean. The experimental results and comparison experiments demonstrate that the presented RTDAQS can reach a sampling rate of 2 GSPS and a sampling resolution of 14 bits and a sampling accuracy of 6 LSB with an acquisition error within 0.1 m, which meet the demands of high sampling rate with high accuracy data acquisition and quick data transmission in practice and can be applied to various devices.

Comparative Study of High Speed ADCs

With the development of information technology, analog-to-digital converter (ADC) is widely used. In products such as radar, ultra wideband communication system, high-performance digital oscilloscope and so on, the speed performance of analog-to-digital converter is usually the bottleneck of the whole system performance, so the research of high-speed ADC has attracted much attention. ADC is an interface circuit that converts analog signals into digital signals that can be processed by DSP. This paper will start with the basic knowledge of ADC, explain the general working process of ADC, introduce several architectures and working principles suitable for high-speed ADC, and compare and analyze their advantages and disadvantages.

Wideband spectrum sensing using step-sampling based on the multi-path nyquist folding receiver

Wideband spectrum sensing with a high-speed analog-digital converter (ADC) presents a challenge for practical systems. The Nyquist folding receiver (NYFR) is a promising scheme for achieving cost-effective real-time spectrum sensing, which is subject to the complexity of processing the modulated outputs. In this case, a multipath NYFR architecture with a step-sampling rate for the different paths is proposed. The different numbers of digital channels for each path are designed based on the Chinese remainder theorem (CRT). Then, the detectable frequency range is divided into multiple frequency grids, and the Nyquist zone (NZ) of the input can be obtained by sensing these grids. Thus, high-precision parameter estimation is performed by utilizing the NYFR characteristics. Compared with the existing methods, the scheme proposed in this paper overcomes the challenge of NZ estimation, information damage, many computations, low accuracy, and high false alarm probability. Comparative simulation experiments verify the effectiveness of the proposed architecture in this paper.

Least-Squares Equalizer Demonstrations Using a Full-Digital Bandwidth Sub-Nyquist-Sampled Wideband Beamformer on an RFSoC

The radio frequency system-on-a-chip (RFSoC) has recently become a viable candidate for completely replacing traditional analog and digital front ends, facilitating the development of wideband phased-array systems where the modern-day RFSoC takes the comprehensive, dominate role in the architecture of the array. Wideband phased-array systems require high-fidelity compensation techniques capable of correcting imbalanced and dispersive channel effects for effective beamforming. This article provides solutions to these challenges by designing a wideband equalizer for a sub-Nyquist-sampled 1.6-GHz <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">S</i> -band phased-array system implemented on a Xilinx 8-channel RFSoC, whose analog-to-digital converters (ADC) operate at 4 gigasamples per second. In brief, an RFSoC is a unique, state-of-the-art, highly integrated device that incorporates a field programmable gate array, high-speed ADCs and digital-to-analog converters with a system-on-a-chip architecture on a single monolithic device. By definition, true time delay beamsteering can be implemented digitally via a combination of integer-sample delays and fractional-sample delay finite impulse response filters. By modifying the filter structure of the fractional-sample delay filter bank to support complex coefficients, channel equalization is integrated with fractional-sample delay filters to mitigate undesired channel effects. For the first time, to the best of our knowledge, this article has developed an equalizer design methodology for an uncalibrated 8-element RFSoC-based sub-Nyquist-sampled wideband beamformer. Lab measurements confirm efficacy.

Broadband Signal Digitization Based on Low-Speed Non-Uniform Photonic Sampling

A new non-uniform photonic sampling (NPS) strategy and its special signal reconstruction algorithm are proposed to achieve digital acquisition of broadband periodic signals at a low sampling rate. Compared with the existing schemes, the NPS strategy can largely reduce the sampling number to acquire identical signal information as that obtained by using its equivalent high-speed uniform photonic sampling, which is beneficial for reducing the sampling time and the data volume of the NPS-based analog-to-digital converter (ADC). In addition, the calculation time of the proposed algorithm is millions of times lower than that of the digital alias-free signal processing (DASP) algorithm used before, which benefits from the fast Fourier transform calculation of a one-dimensional data array instead of a two-dimensional data array calculation in the DASP algorithm. A simulation is performed to validate the feasibility of the proposed scheme. In the simulation, a single-channel NPS-based ADC with an average sampling rate of 1 GSa/s is demonstrated by using the proposed NPS strategy and signal reconstruction algorithm. The results indicate the reconstructed signal information for a single-tone microwave signal at 9.9 GHz and a linear frequency modulation signal in the frequency range of 1 GHz to 9 GHz are identical to those obtained by using its equivalent high-speed uniform photonic sampling-based ADC with a sampling rate of 20 GSa/s.

5 Gs/s 등가 시간 샘플링을 통한 K-Band UWB 레이다 송수신기

In this paper, a K-band complementary metal-oxide-semiconductor (CMOS) ultra-wide-band (UWB) radar is presented. Using an equivalent time sampling technique with a delay-locked loop (DLL), virtual 5 Gs/s high-speed sampling is implemented without using a high-speed analog–digital converter. The receiver comprises a low-noise amplifier, radiofrequency variable amplifier, mixer, and baseband analog, whereas the transmitter comprises switching and driver amplifiers. For the UWB signal, a voltage-controlled oscillator-based impulse generator provides a periodic pulse signal using a switching amplifier controlled by a DLL clock. The proposed UWB radar SoC is fabricated using a 65 nm CMOS wafer, and the measured conversion gain and noise figure of the radar receiver are 79 dB and 7.4 dB, respectively, at 24 GHz. Consequently, we confirm that the measurement of the 11.3 m standard sphere is feasible.

Low Area and High Bit Resolution Flash Analog to Digital Converter for Wide Band Applications: A Review

: This work reviews the design challenges of CMOS flash type Analog-to-Digital Converter (ADC) for making high bit resolution, low area, low noise, low offset, and power-efficient architecture. Low-bit resolution flash ADC architecture, high-speed applications, and wide-area parallel comparators are identified on their suitability of the design for ADCs. These are effective in the area and bit resolution. The overview includes bit resolution, area, power dissipation, bandwidth and offset noise consideration for high-speed flash ADC design. A MUX-based two-step half flash architecture is considered for applications requiring 1 GHz 16-bit resolution low area and low power consumption. An advanced comparator, MUX, a high-speed digital-to-analog converter (DAC), and MUX-based encoder are also reviewed. The design of technology-efficient ADC architecture is highly challenging for the analog designer.