High-speed Digital Interface Research Articles

基于SI分析的高速数字接口拓扑结构设计

为了进一步提高高速数字接口的信号完整性，文章首先介绍了几种常见的高速互连拓扑结构，并对其优劣进行简要的分析，之后利用Cadence SigXplorer PCB SI和Allegro对TMS320C0455和DDR2 (MT47H64M16)之间的高速接口电路拓扑结构进行信号完整性设计，阐述了高速电路设计过程中利用仿真工具对PCB进行前仿真的设计流程，以便于开发人员对此类高速接口的设计。In order to further improve the signal integrity in high speed digital interface, this paper firstly introduces several common high speed interconnect topologies and analyzes their advantages and disadvantages briefly. Then this paper also analyzes the signal integrity of high speed interconnect topology between TMS320C0455 and DDR2 (MT47H64M16) using SigXplorer PCB SI and Allegro and explains the design process of pre-simulation by tools of simulation in high speed circuit design. It will be helpful for designers to such high speed interface.

A Single-Chip 8-Band CMOS Transceiver for 3G Cellular Systems with Digital Interface

In this paper, a single-chip dual-mode 8-band 130nm CMOS transceiver including A/D/A converters and digital filters with 312MHz LVDS interface is presented. For a transmitter chain, linear direct quadrature modulation architecture is introduced for both W-CDMA/HSDPA (High Speed Uplink Packet Access) and for GSM/EDGE. Analog baseband LPFs and quadrature modulators are commonly used both for GSM and for EDGE. For a direct conversion receiver chain, ABB (Analog Base-Band) blocks, i.e., LPFs and VGAs, delta-sigma A/D converters, and FIR filters are commonly used for W-CDMA/HSDPA (High Speed Downlink Packet Access) and GSM/EDGE to reduce chip area. Their characteristics can be reconfigured by register-based control sequence. The receiver chain also includes high-speed DC offset cancellers both in analog and in digital stage, and the self-contained AGC controller, whose parameters such as time constant are programmable to be free from DBB (Digital Base-Band) control. The transceiver also includes wide-range VCOs and fractional PLLs, an LVDS driver and receiver for high-speed digital interface of 312MHz. Measured results reveal that the transceiver satisfies 3GPP specifications for W-CDMA/HSPA (High Speed Packet Access) and GSM/EDGE.

Focus on Analytical Instruments

Focus on Analytical Instruments

Estimation of signal-to-noise ratio improvement in RF-interconnect

RF-interconnect (RFI) can greatly improve the signal-to-noise ratio (SNR) in a high-speed digital interface system by separating the data and the noise in the frequency domain and suppressing the switching noise by the highpass channel characteristics. Experimental characterisation results are presented of a prototype multi-I/O RFI channel. The potential SNR improvement is estimated to be 10 dB compared to conventional digital interface systems. The improved system SNR can lead to enhanced data rate with reduced signalling level in RFI.

1.1 Gbit/s RF-interconnect based on 10 GHz RF-modulation in 0.18 μm CMOS

An RF-interconnect transceiver based on the RF-modulation and capacitive coupling for a high speed digital interface is presented. The prototype transceiver is implemented in 0.18 /spl mu/m CMOS technology. It demonstrates a maximum data rate of 1.1 Gbit/s with a 10 GHz RF-modulation. This RF-interconnect is believed to be instrumental for high-speed link applications in multi-memory and microprocessor interfaces.

1394 high performance serial bus: the digital interface for ATV

The advent of the digital video revolution has created the need for a high-speed digital interface between consumer electronic devices in the home. Examples of this include the interface between a set-top box, a television, and a DVCR or camcorder using MPEG-2 transport streams, and the control and data between interactive games, computers and other devices. Clearly, an interface that supports the general transfer of data is required. The IEEE 1394 standard provides an optimum solution. This paper discusses our proposed implementation of a 1394 based solution and discusses its capabilities and operation in the interactive consumer ATV environment. >