High-speed Comparator Research Articles

A low-power common-mode insensitive rail-to-rail dynamic comparator for ADCs

This paper presents a low-power, high-speed dynamic comparator with a rail-to-rail input common-mode (Vi,cm) range. The proposed comparator has high-speed performance throughout the 0-Vdd Vi,cm range, thus attributing common-mode insensitivity. This work introduces a merger of NMOS and PMOS dynamic pre-amplifiers with a modified latch to achieve the rail-to-rail Vi,cm operation. A novel activation clock logic is also proposed, activating only one pre-amplifier based on the Vi,cm value and ensuring low-power consumption and provides reduction of 17% in the energy per conversion as compared to the comparator without activation clock logic. The proposed comparator is designed using 65-nm CMOS technology with a 1.2 V supply voltage and is operating at 1 GHz frequency. We have presented the analytical models of the delay and offset which is verified with the rigorous post-layout simulation results. To validate the robustness of the proposed comparator, the PVT corner analysis with Monte Carlo simulation is also performed for different Vi,cm.

A high-speed dynamic comparator with automatic offset calibration

A high-speed dynamic comparator with preamplifier and automatic dc offset calibration in all stages is proposed in this paper. The offset compensation is applied in two stages, following a two-part sequential loop training topology, offering significant reduction of the dc offset in each stage. The final resolution is improved with a final value less than 800 μV operating at 7.5 GHz clock speed. The dynamic comparator stage is a double-tail topology while the calibration topology is based on a current injection technique, instead of the commonly used capacitive calibration which can reduce the operating speed. Designed in a CMOS 65 nm technology node, the circuit operates with 1 V supply voltage. Results of PVT Monte Carlo post-layout simulations verify the operation of the proposed topology.

An 8-bit successive-approximation register analog-to-digital converter operating at 125 kS/s with enhanced comparator in 180 nm CMOS technology

Data converters are necessary for the conversion process of analog and digital signals. Successive approximation register (SAR) analog-to-digital converters (ADC) can achieve high levels of accuracy while consuming relatively low amounts of power and operating at relatively high speeds. This paper describes a design of 8-bit 125 kS/s SAR ADC with a proposed high-speed comparator design based on dynamic latch architecture. The proposed design of the comparator enhances the performance compared to a conventional dynamic comparator by adding two parallel clocked input complementary metal-oxide semiconductor (CMOS) transistors which reduce the parasitic resistance in the latch ground path and serve to minimize the latch delay time. The design of each sub-system for the ADC is explained thoroughly, which contains a sample and hold circuit, successive approximation register, charge redistribution types digital-to-analog converter, and the new proposed comparator. The proposed design is implemented using 180 nm CMOS technology with a power supply of 1.2 V. The average inaccuracy in differential non-linearity (DNL) is +0.6/−0.8 LSB (least significant bit), and integral non-linearity (INL) is +0.4/−0.7 LSB. The proposed design exhibits a delay time of 157 ps at 1 MHz clock frequency.

Low-power, high-speed comparator design at 45-nm CMOS for efficient deep learning acceleration

Low-power, high-speed comparator design at 45-nm CMOS for efficient deep learning acceleration

Simplified 1.5 μm Distributed Feedback Semiconductor Laser (DFB-LD) Frequency Stabilization System Based on Gas Absorption Chamber

The classical 1.5 μm band frequency-stabilized laser using acetylene gas saturated absorption can achieve high frequency stability and reproducibility, but its system design is complex and bulky. For some practical applications, a simple, compact system containing anti-interference abilities is preferred. In this study, a low-cost and simple-structured 1.5 μm frequency-stabilized laser is constructed using digital control methods, wavelength modulation technology, and acetylene gas absorption. The fiber input and output optical devices of the system significantly simplify the optical path and reduce the volume of the system. The error signal is obtained by the first-order differential method, and a combination of the high-speed comparator circuit and the microcontroller unit (MCU) is used to detect the error signal. Through the feedback control method of coarse temperature adjustment and fine current adjustment, the second-level frequency stability of the laser is stabilized within 100 kHz, that is, the frequency stability reaches 10​−10. The designed system achieved continuous and stable operation for more than 6 h, and the long-term frequency stability reached 10​−9.

High-speed cascode cross-coupled CMOS dynamic comparator with auxiliary inverter pair

A dynamic comparator is the core element in high-speed, high-resolution analog-to-digital converters (ADCs) used for communication applications. The majority of the dynamic comparators can only operate at high speeds when the input difference voltage is large enough. Due to the limited pre-amplifier gain, the comparators’ performance deteriorates at lower input difference voltages, which is not suitable for high-speed, high-resolution ADCs. A double-tail dynamic comparator with a pair of auxiliary inverters is proposed to alleviate this problem. With the proposed comparator, the pre-amplifier’s differential gain is increased, and the latch regeneration time is reduced by the auxiliary inverter pair resulting in faster comparison operations. The proposed comparator is designed, simulated, and compared with the latest topologies in 65 nm CMOS technology. The performance metrics such as delay, kickback noise, energy consumption per bit, rms noise, and power delay product are evaluated and compared with the state-of-the-art architectures. The proposed technique can be applied to any dynamic comparator that has differential signals at the output of the pre-amplifier stage. Simulations show that the auxiliary inverter pair improves the comparator’s speed by more than 10%.

A rail-to-rail high speed comparator with LVDS output in 0.18-[formula omitted]m SiGe BiCMOS Technology

Achieving low propagation delay in comparators under low input overdrive voltage is challenging. To overcome this difficulty, this paper presents a novel rail-to-rail high-speed comparator. By clamping the output node of the current summation circuit relative to a fixed level VC, the overdrive recovery time under large signal is successfully reduced. Moreover,by adopting a cascaded approach with multiple stages of high bandwidth and low gain,not only is the comparator’s gain enhanced,but it also acquires higher bandwidth. Ultimately, the comparator’s output is transmitted at high speed through an LVDS interface. This design is implemented using 0.18μm SiGe BiCMOS technology. Simulation results show that the comparator has a static power consumption of 26.4 mW, and for 5 mV input overdrive, the average propagation delay is about 1.09 ns.

Review on High-Speed Dynamic Comparators for Analog to Digital Converters

This paper presents a comprehensive review of the state-of-art high-speed dynamic comparators. The comparator is a critical block of high-speed, low-power analog-to-digital converters, determining the speed and overall power consumption. Therefore, the design of a high-speed comparator with tolerable offset, noise and power consumption is of utmost importance. Recent work reported on high-speed comparator topologies is investigated in detail with the help of simulations in 65[Formula: see text]nm CMOS technology. Various parameters, such as delay, energy consumption, speed, offset, kickback noise, power delay product, etc., are compared. A detailed comparative study is also presented on several design methodologies.

Design and analysis of 4-bit absolute-value comparator in 65nm technology using hybrid TG/CMOS

Comparators are an important part of the calculator architecture, and rapid advances in semiconductor and electronics technology have placed higher demands on their performance. Optimization of digital systems involves several levels in order to make improvements in their power consumption, delay, and other parameters. This paper designs a low-power, high speed, and area efficient 4-bit absolute-value comparator, which utilizes a static Complementary Metal-Oxide-Semiconductor (CMOS) and Transmission Gate (TG) hybrid structure. The design optimizes the system at the level of separate circuit blocks, logic gates and transistors. The logic functions are realized by means of transcoding and magnitude Comparison, and the input signals are all driven by two-stage inverters. MUX and XOR with excellent performance of TG structure are implemented using simulation and analysis. In this paper, the transistor sizes and supply voltages of each logic gate are calculated and optimized using MATLAB by applying logic effort theory. The design uses a 65nm technology, and transient simulation of the overall system in Cadence successfully realizes its logic functions with 0.83ns delay and 49.6uw power consumption, proving the effectiveness of the design. This study based on theoretical calculations and simulations is a good reference for the design and theoretical study of very large-scale integrated circuits (VLSI).

High Speed and Area Efficient Scalable n-Bit Digital Comparator

Abstract: The digital comparator is a crucial design element in various applications, including scientific computations. It is optimized for general-purpose computer architecture, memory addressing logic, queue buffers, and test circuits. High-speed comparators are essential for arithmetic operations, data sorting, and decision-making processes in digital systems. Area efficiency is crucial in integrated circuit design, as it minimizes the physical space a comparator occupies on a chip, reducing manufacturing costs and optimizing performance. The term "scalable" means the comparator can be adapted to handle different word lengths (n-bit), making it versatile for various applications. This project proposes an area-efficient n-bit digital comparator with high operating speed and low-power dissipation. The comparator structure consists of two modules: the Comparison Evaluation Module (CEM) and the Final Module (FM). The CEM involves the regular structure of repeated logic cells used for parallel prefix tree structure, while the FM validates the final comparison based on results from the CEM. The design is implemented using Tanner EDA in 45nm technology

1.8-V Low Power, High-Resolution, High-Speed Comparator With Low Offset Voltage Implemented in 45nm CMOS Technology

1.8-V Low Power, High-Resolution, High-Speed Comparator With Low Offset Voltage Implemented in 45nm CMOS Technology

High-Speed and Area-Efficient Serial IMPLY-Based Approximate Subtractor and Comparator For Image Processing and Neural Networks

High-Speed and Area-Efficient Serial IMPLY-Based Approximate Subtractor and Comparator For Image Processing and Neural Networks

Design and analysis of a high-speed low-power comparator with regeneration enhancement and through current suppression techniques from 4 K to 300 K in 65-nm Cryo-CMOS

This paper presents a high-speed low-power cryogenic CMOS two-stage dynamic comparator for SAR ADC. The pre-amplifier uses the dynamic bias technique to save power. To increase the output voltage difference of the pre-amplifier, the StrongARM latch is inserted. The proposed latch keeps a cross-coupled inverter to ensure good positive feedback. The tail current source of the proposed latch is replaced by the input pair to suppress the through current. The auxiliary input pair enhances the gain and positive feedback to speed up the latch. The paper also presents a delay analysis of the dynamic bias technique, which gives a deep understanding and a good intuition for circuit design. The simulation results demonstrate the proposed comparator achieved a CLK-Q delay of 162.1 ps and 295.4 ps at Vid = 1 mV and VCM = 0.7 V with VDD = 1.2 V and fs = 1 GHz in 300 K and 4K. The energy per comparison is 34.04 fJ and 27.75 fJ.

A low power and high speed 45 nm CMOS dynamic comparator with low offset

<p><span lang="EN-US">The development of efficient data converters necessitates the design of low-power and high-speed comparators with low offset. Data converters, such as analog to digital converters (ADCs) and digital to analog converters (DACs), are critical components in applications like wireless communication, multimedia, and sensor interfaces. To enhance the performance of these data converters, improving the speed and power efficiency of comparators becomes crucial. Designing dynamic comparators with low power consumption and high-speed capabilities greatly enhances the sampling rate and accuracy of data converters. Moreover, addressing the offset voltage of comparators becomes crucial for achieving accurate signal conversion. To fulfill this need, a novel dynamic comparator has been designed, featuring high-speed operation, low-power consumption, and minimal offset. The circuit comprises a pre-amplifier with a charge pump, followed by a decision circuit and an output stage. Through simulations, the comparator has demonstrated low power consumption of 15.04 µW, a delay of 80.51 ps, and an extremely low offset voltage of 8 µV. These characteristics make it highly suitable for data converters. The comparator operates at a clock frequency of 1 GHz and a supply voltage of 1 V, and the simulation was conducted using the Cadence Virtuoso tool in a 45 nm CMOS technology.</span></p>

A 1.8 V 115.52 dB Third-Order Discrete-Time Sigma-Delta Modulator Using Nested Chopper Technology

A Sigma-Delta modulator (SDM) realized with a fully differential third-order single-loop cascaded integrator feedforward (CIFF) architecture is proposed. A pair of low-frequency chopper switches are nested outside the chopper amplifier to further reduce the residual offset voltage. To reduce the power consumption and ensure linearity, a high-speed dynamic comparator is also used to implement a one-bit quantizer. The proposed architecture and the corresponding functionality are first simulated in MATLAB Simulink at the behavioral level. The results show that the designed modulator has an SNDR of 124.9[Formula: see text]dB corresponding to an ENOB of 20.46 bits at a clock frequency of 256[Formula: see text]kHz and 312.5[Formula: see text]Hz input with a differential-mode voltage of 700[Formula: see text]mV sinusoidal waveform. Based on SMIC 180[Formula: see text]nm/1.8[Formula: see text]V standard CMOS process on the Cadence platform, the subcircuit-level simulation is also performed, while the result shows that the proposed modulator can effectively achieve 115.52[Formula: see text]dB SNDR, 18.90-bit ENOB, and 8.40[Formula: see text]mW power consumption, which correspond to FoM[Formula: see text] and FoM[Formula: see text] of 0.067[Formula: see text]pJ/step and 163.27[Formula: see text]dB, respectively. The proposed modulator shows a significant advantage to be applied for high-precision analog-to-digital conversion applications such as high-quality equipment for audio, ECG and EEG signal sensing.

OFIDS : Online Learning-Enabled and Fingerprint-Based Intrusion Detection System in Controller Area Networks

As a widely used industrial field bus, the controller area network (CAN) lacks security mechanisms (e.g., encryption and authentication). With the development of network connectivity and the increase in external communication, CAN networks are vulnerable to security attacks (e.g., masquerade). Attackers can intrude on CAN networks to control CAN devices, causing security threats. A fingerprint-based intrusion detection system (IDS) in CAN networks can detect masquerade attacks by scanning the unique clock signals of CAN devices. However, most state-of-the-art fingerprint-based IDSs commonly use an analog-to-digital converter module with a low frequency of 60 MHz to sample CAN signals, lowering the accuracy of the trained fingerprint-based IDS model. In addition, almost all fingerprint-based IDSs are trained offline and then detected online in CAN networks, ignoring that system clock signals of hardware change over time, resulting in degraded detection performance. An intrusion detection system based on physical fingerprints can achieve effective identification of masquerade attacks. This paper proposes an online learning-enabled and fingerprint-based IDS (OFIDS) in CAN networks to increase the sampling frequency, simplify the sampling circuit, shorten the delay time, improve the detection response time, and increase the detection accuracy. OFIDS uses a high-speed comparator (i.e., TLV3501) and field-programmable gate arrays (FPGA; i.e., Xilinx ZYNQ-7010) to sample the CAN_High signal, achieving a low sampling delay time of 4.5 ns and a high sampling frequency of 1 GHz. The self-adaptability of the backpropagation neural network is taken advantage of and used to train the OFIDS model with a detection accuracy of 99.9992%. The OFIDS model is deployed to a CAN network prototype with five CAN devices (i.e., two Arduino UNO boards and three STM32 microcontrollers), where online learning is conducted with a low training time of less than 2 min to update the OFIDS model. Experimental results show that OFIDS can achieve at least 99.99% detection accuracy within 0.18 <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><tex-math notation="LaTeX">$\mu$</tex-math></inline-formula> s in a CAN network prototype and can achieve 98% detection accuracy in a real vehicle.

Designing high-speed and energy-efficient dynamic comparators using complementary carbon nanotube field-effect transistors

Designing high-speed and energy-efficient dynamic comparators using complementary carbon nanotube field-effect transistors

Laser ranging method based on dual-threshold echo pulse prediction and correction

In order to improve the accuracy of pulse laser ranging based on time-of-flight (TOF), this paper proposes a laser ranging method based on double threshold echo pulse prediction correction. By using two high-speed comparators with different thresholds to detect the pulse-echo signal, the initial TOF, pulse width, and edge rate can be obtained. These three parameters are combined with statistical functions to accurately predict the peak position of the echo pulse and obtain the corrected TOF. Finally, the accurate measurement distance is calculated. In the aspect of improving ranging accuracy, this method overcomes the shortcoming that the traditional TOF pulse laser rangefinder has large errors in measuring targets with different reflectivity. This method only uses two high-speed comparators and a monostable trigger more than traditional TOF laser ranging systems. Adding these simple circuits can greatly improve the accuracy of laser ranging. The system structure is simple and the cost is low. Experimental results show that this method can achieve accurate distance measurement, and the measurement error is significantly reduced. This method can greatly improve the performance of the TOF laser rangefinder.

A dynamic power-efficient 4 GS/s CMOS comparator

This paper proposes a mid-stage latch circuit to be employed in a high-speed comparator. The advantages of the proposed circuit are low kickback noise and offset. Moreover, low-power and high-speed characteristics are obtained by avoiding direct connection between the pre-amplifier and latch stages using another stage between them. The power-delay product (PDP) of the comparator is reduced due to the reduction in charging and discharging delays at the latching nodes. The proposed comparator consumes only 244.19 µW using a 1 V supply voltage. Furthermore, the bandwidth, delay, offset, and kickback noise of the proposed comparator are 4 GHz, 26.91 ps, 3 mV, and 38 mV, respectively. Results indicate the proper performance of the proposed comparator in low-power applications.

Investigation of Transient Dose-Rate Effect on High-Speed Comparator SB9696

This paper investigates transient dose-rate effect (TDRE) on a high-speed comparator (SB9696), combining both experimental and simulation methods. Experimental results show that this comparator has two main kinds of transient responses under pulsed gamma-ray environment. First, when the total dose per pulse is less than 54.9 rad(Si), only a short disturbance appears and recovers within several microseconds. Second, when the total dose is beyond 399.6 rad(Si), the comparator is shortly interrupted and then recovers to an under-voltage operation state after several microseconds, and the under-voltage state has a long duration before recovering to a normal working state, which is an uncommon phenomenon that has not been found previously for comparators. A hypothesis is proposed that the short disturbance or interrupt is mainly caused by local photocurrents in the differential structure of the comparator, while the long under-voltage operation state is related to the global photocurrent with a long duration. Lastly, they are successfully verified by SPICE simulations. Simulation results indicate that the short disturbance or interrupt exactly result from local photocurrents in the differential pairs of the comparator’s output module. And, due to the rail-span collapse effect as the global photocurrent flows through power supply lines, the effective supply voltage of the comparator would decrease, thus resulting in a long under-voltage operation state.