High-speed Bus Research Articles

Next generation space avionics: layered system implementation

Advances in electronics over the past decade have produced major improvements in the power and flexibility of computer systems. Unfortunately current avionics systems for space applications typically have not leveraged these COTS advantages. A decade ago, the state-of-the-art for avionics systems made a step change to the Integrated Modular Avionics (IMA) used in the Boeing 777. This next generation avionics architecture is not based upon traditional Byzantine redundancy structures, but on a truth-based scheme where each element knows when an internal failure occurs and removes itself from the system. IMA utilizes a lock-step microprocessor design that communicates to a COTS Backplane for input/output, and to a Virtual Backplane/spl trade/ (a reliable high-speed serial bus) for intra-system communication. The system functions are implemented using a time and space partitioned operating system. The entire system provides the simplicity of a simplex system, implements the highest level of reliability providing complete flexibility to reconfigure both software applications and hardware interfaces, allows for rapid prototyping using low-cost COTS hardware, and is easily expandable beyond the initial point implementation. As the only 5/sup th/ generation avionics architecture, the concepts incorporated into Honeywell's IMA are ideally suited to be the backbone of the next generation Space Exploration Program avionics architectures.

Worst case crosstalk noise for nonswitching victims in high-speed buses

Considering a RLC interconnect model, we determine switching patterns and switching times of multiple aggressors to generate the worst case crosstalk noise (WCN) for a quiet or a noisy victim. We consider the routing direction as it has a significant impact under the RLC model. When there are no timing window constraints, we show that the commonly used superposition algorithm results in 15% underestimation on average, and propose a new SS + AS algorithm that has virtually the same complexity as the superposition algorithm but has a much improved accuracy. On average, the SS + AS algorithm only underestimates WCN by 3% compared to time-consuming simulated annealing and genetic algorithm. We also show that applying a RC model to the high-speed interconnects in the International Technology Roadmap for Semiconductors 0.10 /spl mu/m technology virtually always underestimates WCN, and the underestimation can be up to 80%. Furthermore, we extend our algorithm to consider aggressor switching and victim sampling windows. We show that the extended SS + AS algorithm well approximates WCN with 2% underestimation on average. Although the RC model usually severely underestimates WCN with timing window constraints, it does overestimate when both the aggressor switching and the victim sampling windows are small enough. We conclude that the RLC model is needed for accurate modeling of WCN in design in the multigigahertz region.

Design and validation of a power supply noise reduction technique

For the high-performance microprocessors with high-bandwidth I/O, the power supply noise needs to be controlled to ensure reliable high speed bus operation. This is generally done with high-quality package capacitors. These capacitors are generally lower equivalent series inductance (ESL) and lower equivalent series resistor (ESR). In this paper, we will present two implementations of an approach of using on-die resistors in series with the package capacitance to dampen the high-frequency noise. We will show by validation on the 90-nm technology that this technique is capable of reducing the noise by nearly 80% without adversely affecting the timings. The results of several validation experiments, including the measurement of noise and impedance of the I/O power delivery, and the post-layout simulation will also be presented.

New ECC for Crosstalk Impact Minimization

Signal integrity in high-speed bus designs is put at risk by crosstalk-related bus delays. This article provides a comprehensive study of the usefulness of error correcting code (ECC) redundancy in reducing such delays. It shows that Dual Rail codes perform better at this task than Hamming codes. We describe the modification of DR code that offers some distinct advantages.

A 64-bit microprocessor in 130-nm and 90-nm technologies with power management features

The first two members in a family of 64-bit superscalar microprocessors are presented. The 130-nm processor, which was introduced first, offers 5-way instruction dispatch, support for 4-way integer and floating-point single-instruction multiple-data (SIMD) operations, a 512-kB second level (L2) cache, and a high-speed external bus. The 90-nm processor is a technology remap of the 130-nm design. It retains the features of the 130-nm processor and adds others, including a new power management facility. The architecture, device characteristics, power management, and thermal details of these two processors are described. In addition, the dataflow layout, aspects of the circuit design, clocking, and timing are discussed.

REAL TIME COMPUTING IN A HIGH PERFORMANCE CLUSTER.

Nowadays, cluster computing is a common strategy to achieve high performance computing and resolve computationally intensive tasks such as flight simulation, medical imaging, etc. Two powerful tools have been used to facilitate the development of cluster oriented applications, namely the message passing interface (MPI) and the parallel virtual machine (PVM). However, there are situations in which the application execution is time constrained, e.g., complex real-time image processing, but neither MPI or PVM take time constraints in consideration. Therefore, this paper proposes a cluster integration methodology that is amenable to real-time analysis and implementation, based on Linux with improved temporal resolution and a high-speed TDMA interconnection bus built on top of SCI.The main contribution of the paper is a worst-case response time analysis, its characterization using randomly generated task sets and its verification using a system simulator. The proposed analysis can be applied to a class of distributed real-time systems in which a set of nodes, running tasks under fixed priorities, communicate over a TDMA bus, but it is overly pessimistic in the presence of a significant percentage of communicating tasks.

Exploiting ECC redundancy to minimize crosstalk impact

Signal integrity in high-speed bus designs is put at risk by crosstalk-related-bus delays. This article provides a comprehensive study of the usefulness of error-correcting code (ECC) redundancy in reducing such delays. It shows that dual Rail codes perform better at this task than Hamming codes. We analyze the impact of different ECCs on crosstalk-induced-bus delays (CIBD). We investigate the possibility of exploiting the information redundancy previously necessary to limit CIBD, thus reducing the consequent risk of a system's incorrect operation.

NePSim: a network processor simulator with a power evaluation framework

This article presents NePSim, an integrated system that includes a cycle-accurate architecture simulator, an automatic formal verification engine, and a parameterizable power estimator for NPs consisting of clusters of multithreaded execution cores, memory controllers, I/O ports, packet buffers, and high-speed buses. To perform concrete simulation and provide reliable performance and power analysis, we defined our system to comply with Intel's IXP1200 processor specification because academia has widely adopted it as a representative model for NP research.

Low power high-speed multithreshold voltage CMOS bus architectures

Low power, high-speed bus architectures, based on low swing voltage technique, using multithreshold voltage transistors are proposed in this paper. Three different classes of driver/repeater/receiver circuits are introduced. The driver circuits are comprised of high threshold voltage MOSFET transistors, in order to reduce their output swing level voltage. For re-pulling up the low swing voltage to full swing, innovated high-speed, cross-coupled latch, voltage receiver circuits are used. In applications having high load capacitance due to long interconnections, novel repeater circuits based also on multithreshold voltage technology are introduced. Using 0.5 μm multithreshold voltage process technology and 1 V supply voltage, SPICE measurements showed up to 45% improvement in the power delay product.

Low power high-speed multithreshold voltage CMOS bus architectures

Low power, high-speed bus architectures, based on low swing voltage technique, using multithreshold voltage transistors are proposed in this paper. Three different classes of driver/repeater/receiver circuits are introduced. The driver circuits are comprised of high threshold voltage MOSFET transistors, in order to reduce their output swing level voltage. For re-pulling up the low swing voltage to full swing, innovated high-speed, cross-coupled latch, voltage receiver circuits are used. In applications having high load capacitance due to long interconnections, novel repeater circuits based also on multithreshold voltage technology are introduced. Using 0.5 μm multithreshold voltage process technology and 1 V supply voltage , SPICE measurements showed up to 45% improvement in the power delay product.

The race for real-time Ethernet

Ethernet is starting to replace the industrial fieldbuses that were developed in the 1990s. Not only that it's going after the domain reserved for high-speed fibre optic buses like SERCOS. There are now three proposals for real time Ethernet. Two are from German companies, Siemens and Beckhoff, and the third is from B&R Automation, based near Salzburg. We endeavor to give some idea of how these three real-time Ethernet proposals work.

On the buses [high-speed serial bus

The physical limitations of parallel bus technology are now the principal constraint on computer performance. However, towards the end of 2004, the first of the new generation of PCs incorporating the latest high-performance serial buses will come into use. The new buses will enable PCs to be more compact, powerful and cost-effective. What is more, the ramifications of these changes are extending beyond the confines of the PC into the embedded system market where some of the latest telecoms systems are already using the new serial buses to great effect.

An alignment insensitive separable electromagnetic coupler for high-speed digital multidrop bus applications

A separable electromagnetic coupler was designed, simulated, fabricated, and tested as part of a prototype eight-module multidrop memory bus. The coupler consists of broadside coupled traces, one on a rigid motherboard and the other on a flex circuit soldered to a daughter card. The zig-zag geometry of the traces reduces variation in the coupling coefficient due to horizontal and vertical misalignment of the coupler halves. Simulation and testing indicates that a target capacitive coupling coefficient of 0.34, which has been selected to balance signal-transmission-level requirements against motherboard impedance discontinuity effects, can be achieved with little variation over +/-12-mil alignment tolerance. In addition, custom interface circuitry was designed in conjunction with the coupler to enable 1.6-Gb/s data rate per differential pair. The prototype system was tested for an extended period executing read and write memory transactions for an estimated bit error rate less than 2.0e-17.

Interchip optical interconnection using planar‐type photonic circuit and optoelectronic integrated devices

AbstractElectrical interconnection on printed circuit boards and other peripheral technologies cannot keep up with decreasing interconnection dimensions and increasing driving clock speed in LSI technology, so that system performance is degraded. This “I/O bottleneck problem” has been recognized as a serious threat in the near future. Optical interconnection has drawn attention as a breakthrough technology to resolve this problem. The authors have been engaged in development of optical interconnection technologies that are capable of providing high‐speed and large‐capacity bus lines connecting spatially separated LSI chips on a printed circuit board. This paper explains the photonic circuit configuration and element technologies for interchip optical interconnection by means of a planar photonic substrate with diffractive optical devices and LSI chips integrated with optical devices. The experimental results obtained to date are introduced. © 2002 Wiley Periodicals, Inc. Electron Comm Jpn Pt 2, 86(1): 9–17, 2003; Published online in Wiley InterScience (www.interscience.wiley.com). DOI 10.1002/ecjb.10024

The Level-2 muon trigger at D0

The upgraded DO detector at the Fermilab Tevatron will feature a new three-level trigger based on physics object recognition. The Level-2 muon trigger is required to use the timing data from the muon wire chambers and scintillator to rind track segments and then match those segments with Level-1 muon and fiber tracker trigger information. To accomplish this task, the Level-2 muon trigger features a three-stage approach. The first stage uses a parallel set of custom VME cards that route data through a high-speed and configurable bus to a series of 200-MHz Texas Instruments digital signal processors. This will reduce the large data volume distributed over some 140 sources to a manageable set of three-dimensional track stubs from the 16 cards. Data from these boards are combined to form muon track candidates in the second stage using another custom board built around a 500-MHz Compaq Alpha processor chip. In the third stage, another Alpha-based board matches the muon tracks with tracks found in the central tracking trigger and is able to correlate those muons with other physics objects in the event, such as jets. Queueing simulations of the system running at a rate consistent with the expected input rate and desired background rejection have shown that the Level-2 muon trigger will produce a dead time less than 5%.

Focus on Data Acquisition

Focus on Data Acquisition

The circuit and physical design of the POWER4 microprocessor

The IBM POWER4 processor is a 174-million-transistor chip that runs at a clock frequency of greater than 1.3 GHz. It contains two microprocessor cores, high-speed buses, and an on-chip memory subsystem. The complexity and size of POWER4, together with its high operating frequency, presented a number of significant challenges for its multi-site design team. This paper describes the circuit and physical design of POWER4 and gives results that were achieved. Emphasis is placed on aspects of the design methodology, clock distribution, circuits, power, integration, and timing that enabled the design team to meet the project goals and to complete the design on schedule.

High-speed multi-input VME bus data acquisition system

A data acquisition module, developed under a modularorganizational architecture with links to an object-oriented designapproach, is described. The module comprises four independent 250 MHzeight-bit data acquisition channels and a DSP, each channel controlling alarge memory pool for converted data and supporting several trigger andoperating mechanisms. The hardware, although complex, is completelycontrolled through a set of hierarchically organized classes, making use ofthe object-oriented programming paradigm to keep complexity (from theuser's and programmer's points of view) to a minimum.The integration of the module in the data acquisition system of thereflectometry diagnostic in tokamak ASDEX-Upgrade is described, showing thehardware in regular use and the validity of the object-oriented interfacedeveloped for programming.

SMC

The article presents the SMC system. SMC can be used for checking safety and liveness properties of concurrent programs under different fairness assumptions. It is based on explicit state enumeration. It combats the state explosion by exploiting symmetries of the input concurrent program, usually present in the form of identical processes, in two different ways. Firstly, it reduces the number of explored states by identifying those states that are equivalent under the symmetries of the system; this is called process symmetry . Secondly, it reduces the number of edges explored from each state, in0 the reduced state graph, by exploiting the symmetry of a single state; this is called state symmetry . SMC works in an on-the-fly manner; it constructs the reduced state graph as and when it is needed. This method facilitates early termination, speeds up model checking, and reduces memory requirements. We employed SMC to check the correctness of, among other standard examples, the Link Layer part of the IEEE Standard 1394 “Firewire” high-speed serial bus protocol. SMC found deadlocks in the protocol. SMC was also to check certain liveness properties. A report on the case study is included in the article.

信号伝送線路の特性により生じる波形歪みの解析と低消費電力型バス回路の高速化

信号伝送線路の特性により生じる波形歪みの解析と低消費電力型バス回路の高速化