High-speed Array Research Articles

High-speed iterative array for binary multiplication

An iterative array for the multiplication of binary numbers and also the addition of either one or two other numbers is proposed, employing r.o.m.s. as lookup tables. The regularity of this array should make it attractive for l.s.i. fabrication.

Application of Uniform Loading Theory to Circuit Packaging and Memory Arrays in High-Speed Computers

The uniform loading theory [1] has been approximated and used to analyze a class of interconnection problems usually encountered in the design of high-speed circuit packaging and memory arrays in today's computers. The uniform loads are, for example, IC gates and via holes on multilayered printed circuit board and cross-coupling capacitance in memory arrays. They are treated as discrete loads along smooth transmission lines. The input and output transfer function, impulse response, unit step response, and propagation delay are calculated. To a first-order approximation, the pure resistive loaded line impedance and voltage reflection coefficient can be easily derived. Matching conditions and some experimental results are included. Oscillation due to second-order effects is also discussed.

A 40-ns 17-Bit by 17-Bit Array Multiplier

A high-speed array multiplier generating the full 34-bit product of two 17-bit signed (2's complement) numbers in 40 ns is described. The multiplier uses a special 2-bit gated adder circuit with anticipated carry. Negative numbers are handled by considering their highest order bit as negative, all other bits as positive, and adding negative partial products directly through appropriate circuits. The propagation of sum and carry signals is such that sum delays do not significantly contribute to the overall multiplier delay.