High-radix Algorithm Research Articles

Digit Serial Methods with Applications to Division and Square Root

We present a generic digit serial method (DSM) to compute the digits of a real number $V$ . Bounds on these digits, and on the errors in the associated estimates of $V$ formed from these digits, are derived. To illustrate our results, we derive such bounds for a parameterized family of high-radix algorithms for division and square root. These bounds enable a DSM designer to determine, for example, whether a given choice of parameters allows rapid formation and rounding of its approximation to $V$ .

FPGA Implementation of FFT Architecture using Modified Radix-4 Algorithm

This paper presents an area efficient multiplier less parallel radix 4 Decimation In Frequency-Fast Fourier Transform (DIF-FFT) processor using Distributed Arithmetic Algorithm (DAA). Many numbers of complex computations involved in the radix-2 algorithm have driven to the usage of higher radix algorithms such as radix 4 and radix 8. DAA is an appropriate technique for eliminating the complex multiplications in FFT/IFFT processor by using look-up tables (LUTs) and shift-accumulators. Higher radix FFT algorithm along with DAA provides low area high-speed FFT/IFFT processor. The proposed multiplier less 64 point radix 4 FFT/IFFT processor using DAA algorithm is designed, implemented and simulated in Altera DE2 EP2C35F672C6 device. Hardware implementation of the proposed DAA based 64 point FFT processor has a total of 2.77% FPGA utilization which is 36.62% lesser than conventional FFT/IFFT processors and it operates at 46.30Gbps.

FFT/IFFT Processor for Ultra Wide Band Application

In this paper, a novel 128-Point FFT/IFFT processor for OFDM-based UWB system has been proposed. In proposed MRMDF (Mixed Radix Multipath Delayed Feedback) architecture, high throughput rate can be achieved by using four data paths. Furthermore, the hardware costs of memory and complex multiplier can be saved by adopting delay feedback and data scheduling approaches. In addition, the number of complex multiplications is reduced effectively by using a higher radix algorithm. The measurement results show that the throughput rate of this test chip is up to 1Gsample/s while it dissipates 175mW. When the throughput rate of our processor meets UWB standard, it only consumes 77.6 mW and multiplexers. The features of the proposed MRMDF architecture are the following:• Higher throughput rate can be provided by using four parallel data paths;• The minimum memory is required by using the delay feedback approach to reorder the input data and the intermediate results of each module.• The 128-point mixed-radix FFT/IFFT algorithm is implemented to power consumption.• The number of complex multiplier is minimized by using the scheduling scheme and the specified constant multipliers.

Implementation of very high radix division in FPGAs

A new approach in multiplication-based dividers for FPGAs is proposed. It relies on very high radix algorithms with prescaling of divisor and dividend. The required multiplications (prescale factor computations, divisor prescaling, dividend prescaling, and the division main iteration) are performed using a simplified version of a multiply–add fused unit, which integrates well into the FPGA specific structure. It is shown that the proposed implementation uses a small number of DSP blocks (three for IEEE simple precision, five for IEEE double precision and eight for IEEE quad precision for Spartan 6 devices), in order to perform the division.

Improvement to Montgomery Modular Inverse Algorithm

After a comprehensive study on the Montgomery modular inverse algorithm and its revised versions, two modified high radix algorithms are proposed which utilize higher radix to reduce iterations needed without increasing complexity much, thereby accelerating the process. The radix-4 algorithm can reduce the average number of iterations from 1.4 n to 0.82 n and a software experiment shows the speedup is about 11 percent and iterations are 41.5 percent less on average. The radix-8 algorithm can reduce the average number of iterations to 0.73 n, but it is more complicated, which makes it suitable only for very large numbers (2,048 bits) in the experiment, where the speedup can be 13-18 percent. The proposed algorithms are suitable for software implementations on general-purpose microprocessors

Comments on "A 64-point Fourier transform chip for video motion compensation using phase correlation"

For the original paper see ibid., vol. 31, no. 11, p. 1751-61 (Nov. 1996). The commenter states that the fast Fourier transform (FFT) processor of the aforementioned paper by C.C. Hui et al., contains many interesting and novel features. However, it is pointed out that bit reversed input/output FFT algorithms, matrix transposers, and bit reversers have been noted in the literature. In addition, lower radix algorithms can be modified to be made computationally equivalent to higher radix algorithms. Many FFT ideas, including those of the above paper, can also be applied to other important algorithms and architectures.

NONRESTORING RADIX-2k SQUARE ROOTING ALGORITHM

This paper presents a new high radix square rooting algorithm where a number of square root bits (one digit) are generated in one step. Therefore, the proposed algorithm offers a higher speed than that of the conventional bit parallel binary one. This algorithm can be considered as a generalisation of the conventional bit parallel binary algorithm, and therefore it can be implemented using the existing simple binary elements. The proposed algorithm makes use only of the odd values of the square root to generate the possible values of the radicand and therefore, it requires less area than the conventional restoring high radix algorithm which uses all the values of the square root. This algorithm is general for any radix. Any adder can be used in the basic cell, it can be a carry ripple adder or a carry lookahead adder. As an example of a radix-2k square root architecture, a 9-bit radix-23 architecture is presented in this paper.

Parallel Multiplicative Algorithms for Some Elementary Functions

This correspondence presents generalized higher radix algorithms for some elementary functions which use fast parallel m-bit multipliers where radix = 2m. These algorithms are extensions of those iterative schemes which are based on multiplications by (1 + 2-i) and the use of prestored values of ln (1 + 2-i) and tan-1(2-i). The particular functions under consideration are y/x, y/x1/2, y. exp (x), y + 1n (x), sin (x) and cos (x) [and hence tan (x)]. The extended algorithms rely on multiplication by (1 + d i r-k) where d i , 0 ≤ d i r, is an m-bit integer. Using a simple selection procedure for di, simulations show that p(radix r) digits of a function may be generated, on the average, in less than p + 1 iterations.

A serial minded FFT

An FFT algorithm is presented that can be implemented with serial-access memory. For clarity and insight the emphasis is upon conciseness and illustration rather than shorthand mathematical notation. The algorithm's potential for high-speed implementation is demonstrated by studying variations on the basic algorithm that include both higher radix algorithms and parallel arithmetic unit algorithms. The fact that these sophisticated variations can be seen and understood by inspection of the basic algorithm emphasizes its simplicity. The algorithm is shown very suitable for efficient special-purpose implementation by the functional independence of the transform node from the particular node in the transform or the number of nodes in the transform, i.e., one node in canonical form (for a given radix) represents the entire FFT algorithm. The algorithm is shown to perform variable length transforms at full operational efficiency with minor modification, thus emphasizing its relative versatility. The possibly unexpected conclusion is made that the FFT implementation using parallel arithmetic units is more efficient in terms of speed and probably design effort and hardware, than one using high radix algorithms.

FFT organizations for high-speed digital filtering

The subject of this paper concerns the analysis of high-radix FFT algorithms appropriate to hardware implementation of nonrecursive filters and the error propagation properties associated with these algorithms. Variations in the structure of high-radix fast Fourier transforms are illustrated by means of their Kronecker product expansions. The implications in hardware design of the different structures are discussed. These implications include tradeoffs between memory size and throughput rate as shown by Comparison of the logic organizations of serial and cascade fast Fourier processors. It is shown that in a high-radix cascade processor, significant reduction in memory can often be obtained with a modest increase in complexity of the arithmetic units. The relationship between the permutation matrices specified in a Kronecker factorization, and the structure and addressing of memory is brought out. As an example, the implementation of a nonrecursive digital filter is included using a radix-4 factorization which provides for an extremely simple memory organization. The permutation matrix is such that both data storage and addressing are provided using serial MOS shift registers. In order to compare the accuracy of high-radix algorithms relative to the base-2 algorithm, a fixed-point simulation study of the error propagation properties was conducted of a full radix-4 and a radix-16 FFT for N= 1024 and 256, respectively. The computational errors were compared with corresponding results obtained from the base-2 algorithm. The results of the simulations were also compared with a model which is a modification of that reported by P. D. Welch. The modification consists of the representation of roundoff error buildup in the radix-2 and radix-4 FFT in closed form by a nonhomogeneous difference equation. The illustrative example chosen is the lower bound discussed by Welch.