High-quality Gate Stack Research Articles

Interface Engineering and Gate Dielectric Engineering for High Performance Ge MOSFETs

In recent years, germanium has attracted intensive interests for its promising applications in the microelectronics industry. However, to achieve high performance Ge channel devices, several critical issues still have to be addressed. Amongst them, a high quality gate stack, that is, a low defect interface layer and a dielectric layer, is of crucial importance. In this work, we first review the existing methods of interface engineering and gate dielectric engineering and then in more detail we discuss and compare three promising approaches (i.e., plasma postoxidation, high pressure oxidation, and ozone postoxidation). It has been confirmed that these approaches all can significantly improve the overall performance of the metal-oxide-semiconductor field effect transistor (MOSFET) device.

Gate Stack Engineering for High Temperature Silicon Carbide CMOS ICs

The potential to thermally grow SiO2 on silicon carbide has resulted in it becoming the technology of choice to realise high temperature CMOS circuits. The challenge to achieve a high quality gate stack relies on engineering the metal-insulator-semiconductor interfaces to enable reliable high temperature functionality. Here we describe the effect of different process conditions for the formation of the dielectric layer on the characteristics of the resulting devices. The operating characteristics at elevated temperatures depend critically on the quality of the gate stack. Therefore a systematic evaluation of the intrinsic properties of the gate stack and data from reliability tests are needed.

Direct observation of bias-dependence potential distribution in metal/HfO2 gate stack structures by hard x-ray photoelectron spectroscopy under device operation

Although gate stack structures with high-k materials have been extensively investigated, there are some issues to be solved for the formation of high quality gate stack structures. In the present study, we employed hard x-ray photoelectron spectroscopy in operating devices. This method allows us to investigate bias dependent electronic states, while keeping device structures intact. Using this method, we have investigated electronic states and potential distribution in gate metal/HfO2 gate stack structures under device operation. Analysis of the core levels shifts as a function of the bias voltage indicated that a potential drop occurred at the Pt/HfO2 interface for a Pt/HfO2 gate structure, while a potential gradient was not observed at the Ru/HfO2 interface for a Ru/HfO2 gate structure. Angle resolved photoelectron spectroscopy revealed that a thicker SiO2 layer was formed at the Pt/HfO2 interface, indicating that the origin of potential drop at Pt/HfO2 interface is formation of the thick SiO2 layer at the interface. The formation of the thick SiO2 layer at the metal/high-k interface might concern the Fermi level pinning, which is observed in metal/high-k gate stack structures.

(Invited) Gate Stack and Source/Drain Junction Formations for High-Mobility Ge MOSFETs

Ge is of great interest as a candidate channel material for future CMOS devices due to its high intrinsic carrier mobility. To translate this potential into CMOS, high-quality gate-stack and source/drain (S/D) junction formations are essential. We fabricated Ge n- and p-MOSFETs using the gate-stack formation by bilayer (SiO2/GeO2) passivation and using S/D junction formations by thermal diffusion of P and ion implantation of B. The electron and hole channel mobilities of the fabricated MOSFETs were 1097 and 376 cm2V-1s-1, respectively, despite the very thin GeO2 thickness. We will present the detailed fabrication method and device performance.

(Invited) Direct Observation of Electronic States in Gate Stack Structures: XPS under Device Operation

Although gate stack structures with high-k materials have been extensively investigated, there are some issues to be solved for the formation of high quality gate stack structures. In the present study, we employed hard x-ray photoelectron spectroscopy in operating devices. This method allows us to investigate bias dependent electronic states while keeping device structures intact. Using this method we have investigated electronic states and potential distribution in a Pt gate metal/high-k gate stack structure under device operation. We have found that potential gradient was formed at the Pt/HfO2 interface by analyzing the shifts of the core levels as a function of the applied bias voltage. Angle resolved photoelectron spectroscopy revealed that SiO2 layer was formed at the Pt/HfO2 interface. The formation of the SiO2 layer at the interface might concern the Fermi level pinning, which is observed in metal/high-k gate stack structures.

Fabrication of gate stack with high gate work function for implantless enhancement-mode GaAs n-channel metal-oxide-semiconductor field effect transistor applications

The guidelines for the selection of gate stacks in using an implantless enhancement-mode GaAs n-channel metal-oxide-semiconductor field effect transistor, which is based on a gate material with high work function, are studied using two dimensional device simulation. By employing the silane surface passivation, a high quality gate stack on GaAs substrate comprising of a complementary metal-oxide semiconductor compatible tungsten nitride (WNx) metal gate, which can be easily etched, and a high-permittivity HfAlO gate dielectric is demonstrated. The high work function of 4.97eV and the equivalent oxide thickness of 2.3nm were achieved for this gate stack, which meets the above mentioned normally off operation requirements.

How Trace Analytical Techniques Contribute to the Research and Development of Ge and III/V Semiconductor Devices

Ge and III/V semiconductor substrates are recently being investigated as a candidate material for the replacement of Si substrates in advanced micro-electronic devices. The reintroduction of this material requires engineering of the standard IC processing steps. In this paper, we present how the trace analytical techniques of total reflection X-ray fluorescence spectrometry (TXRF) and atomic absorption spectrometry (AAS) contribute to the realization of suitable processes to realize a high quality gate stack on Ge and GaAs substrates. A conventional application for these techniques lays in contamination control on incoming wafers. Besides this, we demonstrate some more advanced applications such as the determination of dopant concentrations (As in Ge), the study of passivation processes (S on Ge) and the characterization of nanometer thin layers (Si on Ge, HfO2 on Si).