High-purity Semi-insulating 4H-SiC Research Articles

(Invited) SiC Lateral Mosfet Implemented on Semi-Insulating Substrate

In most cases, lateral SiC MOSFETs implemented on a SiC epitaxial layer which grown on off-axis conducting substrate. For 4H-SiC, 4º-off toward <11-20> substrate is widely used in order to avoid polytype inclusion. However, step bunching often occurs during the epitaxial growth and high temperature activation process. The step bunching makes surface rough and causes scattering of carriers at the surface. Consequently, the channel mobility of the lateral MOSFET implemented on epitaxial layer grown on off-axis substrate is reduced. Therefore, on-axis substrate has advantages for improving static characteristics compared to the off-axis substrate. However, it is still possible to create polytype inclusion on an on-axis substrate during epitaxial growth, and elimination of epitaxial layer is preferred in many aspects. In this research, 4H-SiC lateral double implanted MOSFET (LDIMOSFET) have been designed and fabricated on an on-axis high purity semi-insulating (HPSI) substrate for the first time. To avoid the step bunching and polytype inclusion problem, we used on-axis SiC substrate without epitaxial layer. Figure 1 shows a cross-sectional view of the LDIMOSFET. As shown in the figure, proposed LDIMOSFET adopted a current path layer (CPL) instead of an epi-layer of the conventional lateral MOSFET. All regions of the LDIMOSFET were formed by ion-implantation. The CPL region plays an important role in obtaining MOSFET characteristics. At a forward bias condition, the CPL serves as a current path of the device, and at reverse bias condition, it serves to support the breakdown voltage. Without CPL region, only the semi-insulating layer exists between the p-base and n+ drain region. In this case, due to a low concentration of the semi-insulating substrate, small value of forward current will flow. Therefore, for obtaining desired forward and reverse characteristics, it is important to optimize the CPL parameters such as doping concentration (NCPL), depth (DCPL), and length (LCPL). To optimize the CPL parameters, device simulations were performed by using device simulator Silvaco-ATLAS. In order to obtain high breakdown voltage and low specific on-resistance, NCPL and DCPL should be within range of 2 × 1016 ≤ NCPL ≤ 4 × 1016/cm3 and 0.2 ≤ DCPL ≤ 0.3 μm, respectively. For device fabrication, considering the simulation results, we used NCPL = 2 × 1016 /cm3, and DCPL = 0.3 μm, respectively. Breakdown voltage and specific on-resistance are also depends on LCPL. Therefore, to find out the effect of LCPL on the breakdown voltage and specific on-resistance, LCPL was varied from 5 to 20 μm. For device fabrication, on-axis HPSI 4H-SiC wafers were used. To find out the effect of CPL region on the device characteristics, LDIMOSFET without CPL is also fabricated. The extracted channel mobility of the LDIMOSFET is 21.7 cm2/V∙s. The reported mobility of the Al-implanted MOSFETs fabricated on the on-axis epitaxial layer is 9 to 19 cm2/V∙s, and they explain that the mobility increase is due to the lower surface roughness. We used on-axis HPSI substrate to avoid the surface roughness scattering caused by the step bunching and we observed mobility comparable to those measured in the device implemented on the epitaxial grown on the on-axis wafer. Figure 2 shows measured IDS – VDS characteristics of the LDIMOSFET when LCPL = 5 μm. As shown in the figure, the highest drain current is 22mA/mm. In contrast, currents in the LDIMOSFET without CPL slightly increase when drain voltage exceeds 10 V. A specific on-resistance of the LDIMOSFET is 17.2 mΩ∙cm2 at VG = 25 V and VD = 1 V. When LCPL was increased from 5 to 20 μm, the specific on-resistance of the device also increased, from 17.2 to 89.8 mΩ∙cm2. The breakdown voltage of LDIMOSFET depends on LCPL, DCPL, and NCPL. Figure 3 shows measured breakdown voltage for different LCPL. As shown in the figure, longer LCPL shows higher breakdown voltage, and the maximum breakdown voltage of 1093 V was observed when LCPL = 20 μm. Maximum breakdown voltage of 1093 V was achieved with low specific on-resistance of 89.8 mΩ∙cm2 at LCPL = 20 μm. The figure of merit (BV2/Ron,sp) of the fabricated LDIMOSFET is 13.3 MW/cm2. The breakdown voltage and specific on-resistance of the device can be improved by adopting field plate and RESURF principle. The effect of the field plate and RESURF principle is under investigation. We will discuss about the detailed effects of the field plate, RESURF principle and device parameters on the static characteristics of the fabricated LDIMOSFET at the manuscript. Figure 1

Effect of electron avalanche breakdown on a high-purity semi-insulating 4H-SiC photoconductive semiconductor switch under intrinsic absorption.

High-power photoconductive semiconductor switching devices were fabricated from a high-purity, semi-insulating 4H-SiC wafer. A highly n-doped GaN subcontact layer was inserted between the contact metal and the high-resistivity SiC wafer. The minimum ON-state resistance of the device was less than 1ohm when the energy of a 355nm laser was 10.5mJ with a bias voltage of 6kV. The maximum device lifetime is 3151 pulses, after which the device completely fails. The failure mechanisms are determined using several analysis methods. Under a strong electric field, the failure mechanism differs for the two electrodes. Near the edge of the anode electrode, the switch is damaged due to the thermal stress caused by impact ionization. At the edge of the cathode electrode, the electrode erosion is the main reason for the failure to operate for long periods of time. These two different damage mechanisms are both important factors influencing the device performance. The electron avalanche breakdown at the edge of the anode electrode causes the formation of cracks between the electrodes, which is the root cause of the switch failure.

Reliability comparison of 28 V–50 V GaN-on-SiC S-band and X-band technologies

This paper discusses the reliability performance of Wolfspeed GaN/AlGaN high electron mobility transistor (HEMT) MMIC released process technologies, fabricated on 100 mm high purity semi-insulating (HPSI) 4H-SiC substrates. The intrinsic reliability performances of the 28 V and 40 V technologies, with 400 nm and 250 nm gate length, have been characterized with DC accelerated life test (DC-ALT), for which ohmic contact inter-diffusion is the wear-out mechanism, and is accelerated by temperature and current. The intrinsic reliability performance of the 50 V technologies, with 400 nm gate length, have been characterized with RF-ALT, for which source-connected second field plate void coalescence is the wear-out mechanism which is accelerated by temperature. In spite of the differences in the accelerated test methodologies and wear-out mechanisms, all of the Wolfspeed GaN-on-SiC technologies demonstrate high and similar predicted lifetimes at their respective maximum recommended operating conditions. The reliability performance is supported with successful technology qualifications with zero failures, and volume manufacturing with a demonstrated low field failure rate.

D–T Neutron and 60Co-Gamma Irradiation Effects on HPSI 4H-SiC Photoconductors

The 14.1-MeV neutron irradiation- and 60Co-gamma irradiation-produced traps in high-purity semi-insulating (HPSI) 4H-SiC photoconductors (PCs) are reported, and the irradiation-induced changes in substrate resistivity, dark current, and UV response of the 4H-SiC PCs are analyzed. From the zero-bias thermally stimulated current measurements, six new traps at the energy levels $E_{v} \,+\, 0.58$ eV, $E_{v} \,+\, 0.68$ eV, $E_{v}\,+\, (0.7-0.9)$ eV, $E_{c} \, - \,0.64$ eV, $E_{c}\, -\, 0.91$ eV, and $E_{c} \, - \,1.04$ eV are identified in the 14.1-MeV neutron-irradiated PCs at the fluence of 1011 n/cm2, along the defects already detected before neutron irradiation. The thermal activation energy range (1–1.3 eV) for HPSI 4H-SiC is unaffected, and no considerable changes in the UV response of the PCs are noticed after the 14.1-MeV neutron irradiation. On the other hand, in addition to the traps determined prior to the irradiation, one new deep hole trap at $E_{v} + 1.31$ eV and significant changes in the activation energies (1.1–1.35 eV) are observed in the gamma-irradiated PCs at the dose of 100 Mrad, which suggest that the HPSI 4H-SiC substrate resistivity is increased due to the gamma irradiation-produced traps. Moreover, the signal-to-dark current ratio of the PCs is reduced after the gamma irradiation, as inferred from the UV response of the PCs.

Performance of epitaxial and HPSI 4H-SiC detectors for plasma X-ray imaging systems

The room temperature X-ray spectral response of Schottky barrier diodes (SBDs) and bulk detectors on n-type epitaxial 4H-SiC and high-purity semi-insulating (HPSI) 4H-SiC substrates is investigated in the energy range of 30–40 keV for fusion plasma X-ray imaging systems (XIS). The different noise components (in terms of FWHM-equivalent noise energy) of the detector energy resolution are also analyzed. An energy resolution of 3.5 keV FWHM (for 152Eu X-rays), ∼ 90% charge collection efficiency (CCE) at −100 V are obtained with the SBD detectors. The intrinsic detection efficiency of the SBD detectors at 32 keV and 40 keV is found to be 0.42%, and 0.23%, respectively. In SBD detectors, the X-ray produced signal strength is unchanged with time, therefore the polarization phenomenon is not observed. An energy resolution of 11.2 keV FWHM is noted from the 137Cs X-ray spectral response of the bulk detectors. It is found that the X-ray produced signal decreases with time after the bias voltage was applied to the bulk detectors because of the polarization effect; thus CCE and detection efficiency decreases with time. The CCE attained with the bulk detectors at −500 V is not more than 30%. The identified intrinsic efficiency of the bulk detectors is lower than the SBD detectors. Furthermore, to study the reliability the 4H-SiC detectors in a fusion-reactor like environment, 14.1 MeV and 4.5 MeV neutron irradiation effects on the X-ray spectral response of the detectors are analyzed up to a fluence 1011 n/cm2. Based on the present results, the possible application of the 4H-SiC detectors in the fusion XIS is discussed.

Spectroscopic performance studies of 4H-SiC detectors for fusion alpha-particle diagnostics

The spectroscopic performances of Schottky barrier diodes (SBDs) and bulk detectors fabricated on n-type epitaxial 4H-SiC and high-purity semi-insulating (HPSI) 4H-SiC substrates are studied using 241Am alpha-particles. The spectral responses of the SBD detectors reveal a good energy resolution of 55 keV FWHM (∼1%) at −60 V, and ∼90% charge collection efficiency (CCE) at −100 V. The collected signal charge is stable with time in the SBD detectors; hence polarization effects are not noticed, indicating the good crystalline quality of the epitaxial 4H-SiC for detector applications. On the contrary, a poor energy resolution of 675 keV FWHM (12.3%) at −400 V and a maximum CCE of 28% at −500 V are obtained for the bulk detectors. Moreover, the CCE is found to decrease with time after the application of bias voltage implying the polarization phenomenon. Accordingly, the steady-state CCE of the bulk detectors at −500V is decreased to 13% from its initial value. The inferior spectral response of the bulk detectors is possibly due to the charge trapping and polarization effects. Furthermore, the neutron irradiation effects on the α-particle spectral response of the detectors are examined up to a fluence of 1011 n/cm2. To study the reliability of the SBD detectors at higher irradiation levels, the 14.1 MeV neutron irradiation induced changes in the electrical characteristics of the SBD are investigated up to a fluence of 2×1015n/cm2 by device simulations and the probable degradation in the detector response is analyzed. Finally, the possibility of employing 4H-SiC detectors for the fusion alpha-particle diagnostics is discussed.

Current status of modelling the semi-insulating 4H–SiC transient photoconductivity for application to photoconductive switches

In this paper we present the current status of modelling the time evolution of the transient conductivity of photoexcited semi-insulating (SI) 4H–SiC taking into account the properties of defect centres. A comprehensive model that includes the presence of six, the most significant, point defects occurring in SI 4H–SiC crystals is presented. The defect centres are attributed to the two kinds of nitrogen-related shallow donors, a boron-related shallow acceptor, deep electron and hole traps, and the Z 1/2 recombination centre. We present the results of the state-of-the-art numerical simulations showing how the photoconductivity transients change in time and how these changes are affected by the properties of defect centres. The properties of defect centres assumed for modelling are compared with the results of experimental studies of deep-level defects in high purity (HP) SI 4H–SiC wafers performed by the high-resolution photoinduced transient spectroscopy (HRPITS). The simulated photoconductivity transients are also compared with the experimental photocurrent transients for the HP SI 4H–SiC wafers with different deep-level defects. It is shown that a high-temperature annealing producing the C-rich material enables the fast photocurrent transients to be achieved. The presented analysis can be useful for technology of SI 4H–SiC high-power photoconductive switches with suitable characteristics.

Creation and Functionalization of Defects in SiC by Proton Beam Writing

Proton beam writing was carried out into high purity semi-insulating 4H-SiC bulk substrates. Luminescent defects created in the SiC by proton beam writing using 1.7 MeV-proton micro beams were investigated at room temperature using confocal laser scanning microscope. As a result, photoluminescence peak around 900 nm associated with silicon vacancy was observed for the irradiated SiC without post implantation process such as annealing. The overall depth profile of photon counts detected from irradiated areas is in good agreement with simulated vacancy depth profile. This suggests that silicon vacancy can be applied to ion tracking detector. In addition, since silicon vacancy is known as single photon source of which spins can be controlled at RT, PBW is expected to be a useful tool to fabricate spin qubits.

Nonlinear UV absorption properties of bulk 4H-SiC

The intensity-dependent light absorption in bulk high-purity semi-insulating 4H-SiC at above band gap photon energies has been studied. In particular, 3.49 eV (355 nm) UV absorption of 160 μm-thick samples of varying recombination lifetimes in the intensity range of 1 mJ/cm2–30 mJ/cm2 is addressed. The effective absorption coefficient was found to vary up to 30% within this range. Assuming deep level trapping, interband absorption, and free carrier absorption as dominant processes, a four energy level model reproduces the experimentally observed absorption behavior. While nonlinearities in the optical absorption behavior of SiC have been studied previously as function of wavelength α(λ), temperature α(T) and, to a very limited extent, at below bandgap optical intensities, the presented elucidates the UV intensity-dependent nonlinear absorption behavior, α(I), of SiC at above bandgap photon energies.

Electrically Active Defects in Neutron Irradiated HPSI 4H-SiC X-ray Detectors Investigated by ZB-TSC Technique

Electrically active defects in high-purity semi-insulating (HPSI) 4H-silicon carbide (4H-SiC) X-ray detectors have been characterized before and after neutron irradiation by zero-bias thermally stimulated current (ZB-TSC) and high-temperature resistivity measurements. The ZB-TSC measurements prior to irradiation reveal nine hole traps in the energy range of 0.22–1.16 eV and two electron traps at $\text{E}_{c} -0.35$ eV and $\text{E}_{c} -0.44$ eV. For the same case, high-temperature resistivity measurements yield thermal activation energy in the range of 1–1.3 eV. It is considered that the hole traps at $\text{E}_{v}+ 0.83$ eV and $\text{E}_{v }+ 1.16$ eV along with defects located near the activation energies are possibly responsible for the substrate compensation. A poor resolution of 11.8-keV full-width at half-maximum (at 40 keV of 152Eu) with un-irradiated HPSI 4H-SiC detectors is attributed to the charge trapping and polarization effects. After neutron irradiation at the fluence of $10^{11}$ n/cm2, seven new traps ( $\text{E}_{v}+ 0.68$ eV, $\text{E}_{v} + 1.08$ eV, $\text{E}_{v} + 1.22$ eV, $\text{E}_{c} -0.72$ eV, $\text{E}_{c} - 0.9$ eV, $\text{E}_{c} - 1.04$ eV, and $\text{E}_{c} - 1.1$ eV) are identified with no significant changes in the activation energies. This indicates that the substrate resistivity is unaffected by the neutron-irradiation-induced defects. No considerable changes in the X-ray spectral response are noted at $10^{11}$ n/cm2.

Effects of Hydrogen Concentration on the Growth of High Purity 4H-SiC Single Crystal Grown by Sublimation Method

In this paper, the effects of hydrogen concentration on growth rate, micropipe density and nitrogen concentration of 4H-SiC crystals were discussed. It was shown that the growth rate is a linear function of the hydrogen concentration, which can be explained not only by C/Si ratio but also the temperature gradient. It was also found that the micropipe density was increased rapidly when the hydrogen concentration exceed a critical value, because the defects such as Si droplets, carbon inclusions and polytype formation were generated at that time. The results of secondary ion mass spectroscopy (SIMS) showed that with increasing the hydrogen concentration, the nitrogen concentration falls down but reaches a constant value which meets the requirements for high purity semi-insulating (HPSI) SiC single crystal growth. Finally, the HPSI 4H-SiC crystals were obtained using 15% hydrogen concentration, the resistivities of wafers cut from these crystals were more than 109Ω•cm, micropipe densities were less than 5cm-2, the full width at the half-maximum (FWHM) were between 30-40 arcsec, making these wafers suitable for microwave devices fabrication.

Thermal Stability of Deep-Level Defects in High-Purity Semi-Insulating 4H-SiC Substrate Studied by Admittance Spectroscopy

Effects of high temperature treatments on the deep-level defects in high-purity semi-insulating substrates are studied by employing electrical and chemical analyses. Thermal admittance spectroscopy reveals the presence of a deep-level defect, labeled XMID, with a state near the middle of the bandgap, playing a decisive role to realize the semi-insulating characteristics. The concentration of the XMID level decreases with increasing treatment temperature from 1400 to 1700 °C, and consequently, the substrate becomes more conductive toward p-type due to residual boron impurities. The identity of XMID is yet to be known but the carbon vacancy is briefly discussed as a possible candidate.

Polytype Stabilization of High-purity Semi-insulating 4H-SiC Crystal via the PVT Method

Because the conditions under which semi-insulating 4H-SiC crystals can grow are so specific, other polytypes such as 15R and 6H can easily emerge during the growth process. In this work, a polytype stabilization technology was developed by altering the following parameters: growth temperature, temperature field distribution, and C/Si ratio. In the growth process of high-purity semi-insulating 4H-SiC crystals, the generation of undesirable polytypes was prevented, and a crystal 100 % 4H-SiC polytype was obtained. A high C/Si ratio in powder source was shown to be advantageous for the stabilization of the 4H polytype. Several methods were applied to evaluate the quality of crystals precisely; these methods include Raman mapping, X-ray diffraction, and resistivity mapping. Results showed that the 3inch-wafer was entirely made of 4H polytype, the mean value of FWHM was approximately 40 arcsec, and the distribution of the resistivity value was between 106 Ω×cm and 107 Ω×cm.DOI: http://dx.doi.org/10.5755/j01.ms.22.2.12914

High temperature annealing effects on deep-level defects in a high purity semi-insulating 4H-SiC substrate

Effects of high-temperature annealing on deep-level defects in a high-purity semi-insulating 4H silicon carbide substrate have been studied by employing current-voltage, capacitance-voltage, junction spectroscopy, and chemical impurity analysis measurements. Secondary ion mass spectrometry data reveal that the substrate contains boron with concentration in the mid 1015 cm−3 range, while other impurities including nitrogen, aluminum, titanium, vanadium and chromium are below their detection limits (typically ∼1014 cm−3). Schottky barrier diodes fabricated on substrates annealed at 1400–1700 °C exhibit metal/p-type semiconductor behavior with a current rectification of up to 8 orders of magnitude at bias voltages of ±3 V. With increasing annealing temperature, the series resistance of the Schottky barrier diodes decreases, and the net acceptor concentration in the substrates increases approaching the chemical boron content. Admittance spectroscopy results unveil the presence of shallow boron acceptors and deep-level defects with levels in lower half of the bandgap. After the 1400 °C annealing, the boron acceptor still remains strongly compensated at room temperature by deep donor-like levels located close to mid-gap. However, the latter decrease in concentration with increasing annealing temperature and after 1700 °C, the boron acceptor is essentially uncompensated. Hence, the deep donors are decisive for the semi-insulating properties of the substrates, and their thermal evolution limits the thermal budget for device processing. The origin of the deep donors is not well-established, but substantial evidence supporting an assignment to carbon vacancies is presented.

Ion Implanted Lateral p&lt;sup&gt;+&lt;/sup&gt;-i-n&lt;sup&gt;+&lt;/sup&gt; Diodes on HPSI 4H-SiC

Square shaped annular lateral p+–i–n+ diodes on high purity semi-insulating (HPSI) 4H-SiC are fabricated by Al+ and P+ ion implantation to obtain anode and cathode regions, respectively. All the diodes have the same size central anode surrounded by an intrinsic region, which is surrounded by an annular cathode. Anode area and annular cathode width are fixed for all diodes, only the lateral length of the intrinsic region is varied. Post implantation annealing is performed at 1950 °C for 10 min. Static forward and reverse characteristics are measured in the temperature range of 30 - 290 °C. For all diodes, the reverse current is below the instrument detection limit of 10-14 A up to 100 °C at 200 V, the maximum reverse bias employed in this study. The reverse current increased up to low 108 A for 200 V reverse bias at 290 °C. Forward currents overlap at the low voltage region once they exceed the instrument detection limit at ~1.6 V and 30 °C. The forward currents follow almost identical exponential trend at all measured temperatures while the diode series resistance increase with increasing anode-cathode distance and decreased with increasing temperature for the given intrinsic region lateral length.

High Power Lateral Silicon Carbide Photoconductive Semiconductor Switches and Investigation of Degradation Mechanisms

Several generations of high power, lateral, linear mode, intrinsically triggered 4H-SiC photoconductive semiconductor switch designs and their performance are presented. These switches were fabricated from high purity semi-insulating 4H-SiC samples measuring 12.7 mm × 12.7 mm × 0.36 mm and were able to block dc electric fields up to 370 kV/cm with leakage currents less than 10 μA without failure. Switching voltages and current s up to 26 kV and 450 A were achieved with these devices and ON-state resistances of 2 Ω were achieved with 1 mJ of 355 nm laser energy (7 ns FWHM). After fewer than 100 high power switching cycles, these devices exhibited cracks near the metal/SiC interface. Experimental and simulation results investigating the root cause of this failure mechanism are also presented. These results strongly suggest that a transient spike in the magnitude of the electric field at the metal/SiC interface during both switch closing and opening is the dominant cause of the observed cracking.

Plasma Etching of n-Type 4H-SiC for Photoconductive Semiconductor Switch Applications

Photoconductive semiconductor switches (PCSS) fabricated on high-purity semi-insulating 4H-SiC substrates (000\( \bar{1} \)) are capable of switching high currents in compact packages with long device lifetimes. A heavily doped n-type SiC epitaxial layer of appropriate thickness is required to form low-resistance ohmic contacts with these devices. In addition, to enhance the performance of the PCSSs, the SiC surface between the ohmic contacts must be extremely smooth. We report a chlorine-based, inductively coupled plasma reactive ion-etching process yielding n-type SiC epitaxial layers with the required smoothness. The rate of etching and post-etching surface morphology were dependent on plasma conditions. We found that the surface smoothness of epitaxial layers can be improved by including BCl3 in the argon–chlorine mixture. The optimum etching process yielded very smooth surfaces (∼0.3 nm RMS) at a relatively high rate of etching of ∼220 nm/min. This new fabrication approach significantly reduced the on-state resistance of the PCSS device and improved its durability of operation.

The Role of Substrate Compensation on DC Characteristics of 4H-SiC MESFET with Buffer Layer: A Combined Two-Dimensional Simulations and Analytical Study

An analytical model of 4H-SiC metal semiconductor field effect transistor (MESFET) is proposed with buffer layer on high purity semi-insulating (HPSI) 4H-SiC substrate compensated by multiple deep level traps. The contribution of deep level traps (DLT) is projected and verified using two-dimensional simulations (Silvaco®). The modeled DC characteristics are compared with two-dimensional simulations performed on the same device as considered in the analytical model.The 4H-SiC MESFET is simulated with and without the effect of buffer layer and the electron concentration profiles in different regions are observed from two-dimensional simulations.The electron concentration profiles obtained at channel-substrate interface clearly shows that when the buffer layer is not present, the channel electrons get trapped by the deep level traps used for substrate compensation. It is also observed that the inclusion of buffer layer minimizes the extent of electron trapping by screening out the active channel from the substrate. However, the trapping phenomena take place in both the cases.We believe that the proposed model of 4H-SiC MESFET which includes the substrate compensation through multiple deep level traps may be useful for realizing SiC based monolithic circuits (MMICs) on HPSI substrates.

Radiation-Induced Currents in 4H-SiC Dosimeters for Real-Time Gamma-Ray Dose Rate Monitoring

In order to test the response of radiation-induced current with wide range of dose rate, a Silicon Carbide (SiC) dosimeter is exposed to gamma-rays emitted from a60Co source. The SiC dosimeter in this study is made of a high purity semi-insulating 4H-SiC with nickel and aluminum electrodes. We have successfully demonstrated that the radiation-induced currents in the dosimeter show a linear relationship with the dose rate, and are repeatable and stable.

Defect Levels in High Purity Semi-Insulating 4H-SiC Studied by Alpha Particle Induced Charge Transient Spectroscopy

Defect levels in high purity semi-insulating 4H silicon carbide substrates are studied by charge transient spectroscopy using 5.5 MeV alpha particles. A shallow defect level with the activation energy around 0.3 eV is found in all samples annealed at temperatures from 1400 to 1600 °C. Some other defect levels lying at deeper in the bandgap are found in samples annealed at 1400 and 1500 °C. As these deep levels are annealed out by 1600 °C, the series resistance of samples is decreased.