High-purity Semi-insulating 4H-SiC Substrates Research Articles

Effective channel mobility in phosphorus-treated 4H-SiC (0001) metal-oxide-semiconductor field-effect transistors with various p-body doping concentrations

Phosphorus treatment, which can substantially reduce the interface state density (D it), was used to investigate the impact of D it on effective channel mobility (μ eff) of 4H-SiC (0001) metal-oxide-semiconductor field-effect transistors (MOSFETs). A high μ eff of 126 cm2 V−1 s−1, which exceeds the reported phonon-limited mobility of 83 cm2 V−1 s−1 determined from Hall mobility of nitridation-treated MOSFETs, at a high effective normal field of 0.57 MV cm−1 was obtained in MOSFETs fabricated on a high-purity semi-insulating 4H-SiC substrate at room temperature. This high mobility may be caused by the difference of the density of electrons trapped at the interface states.

Carrier Trapping Effects on Forward Characteristics of SiC p-i-n Diodes Fabricated on High-Purity Semi-Insulating Substrates

Carrier trapping effects of high-concentration deep levels in high-purity semi-insulating (HPSI) silicon carbide (SiC) substrates on device characteristics were investigated. Vertical p-i-n diodes were fabricated on HPSI 4H-SiC substrates with ion implantation processes. The fabricated diodes showed good rectification. The experimental forward current&#x2013;voltage (<inline-formula> <tex-math notation="LaTeX">${I}$ </tex-math></inline-formula>&#x2013;<inline-formula> <tex-math notation="LaTeX">${V}$ </tex-math></inline-formula>) characteristics were analyzed by using drift-diffusion (DD) simulation that considers deep levels both as recombination centers and carrier traps. The DD simulation revealed that high-concentration carrier traps flatten the potential distribution in the i-type region and, therefore, increase the recombination current and ideality factor in the low-bias region. The simulated <inline-formula> <tex-math notation="LaTeX">${I}$ </tex-math></inline-formula>&#x2013;<inline-formula> <tex-math notation="LaTeX">${V}$ </tex-math></inline-formula> characteristics assuming a high trap density of <inline-formula> <tex-math notation="LaTeX">$5 \times {10}^{16} \mathrm { \text {cm}^{-{3}}}$ </tex-math></inline-formula> showed good agreement with experimental ones in the temperature range of 295&#x2013;600 K.

High-voltage LDIMOSFETs on HPSI 4H-SiC substrate with dual field plates

High-voltage lateral double-implanted metal-oxide-semiconductor field-effect transistor on high-purity semi-insulating 4H-SiC substrate with dual field-plates on both gate and drain was experimentally demonstrated and analyzed by a simulation method. E-field crowding under gate and drain was successfully suppressed by the optimized dual field-plates so that high breakdown voltage of 1.6 kV was achieved at Ldrift = 20 μm. Also, we obtained a low Ron,sp (specific on-resistance) of 30 mΩ cm2 at Ldrift = 20 μm by shrinking the channel length and controlling doping concentration of a drift region.

SiC Vertical-Channel n- and p-JFETs Fully Fabricated by Ion Implantation

Silicon carbide (SiC) n-and p-channel junction field effect transistors (JFETs) with vertical channels were fabricated by direct ion implantation into a high-purity semi-insulating 4H-SiC substrate in order to further develop the path towards complementary JFET integrated circuits for applications in harsh environments. Compared with the conventional structure (lateral channel), the proposed structure is suitable for integration and inherently has a high transconductance owing to the double-gate configuration. The threshold voltage (Vth) can be controlled by mask design, while Vth in the conventional structure is solely determined by the ion implantation conditions. We demonstrate the transistor operation of the vertical-channel n-and p-channel JFETs fully fabricated by ion implantation.

High-voltage lateral double-implanted MOSFETs implemented on high-purity semi-insulating 4H-SiC substrates with gate field plates

Lateral double-implanted MOSFETs (LDIMOSFETs) fabricated on on-axis high-purity semi-insulating (HPSI) 4H-SiC substrates with gate field plates have been demonstrated for the enhancement of reverse blocking capability. The effects of gate field plate on LDIMOSFET were analyzed by simulation and experimental methods. The electric field concentration at the gate edge was successfully suppressed by a gate field plate. A high breakdown voltage of 934 V and a figure of merit of 14.6 MW/cm2 were achieved at LFP of 2 µm and Ldrift of 15 µm, while those of the conventional device without a gate field plate were 744 V and 13.3 MW/cm2, respectively. Also, the fabricated device shows stable blocking characteristics at a high temperature of 250 °C. The drain leakage was increased by only 22% at 250 °C compared with that at room temperature.

High-Temperature Operation of n- and p-Channel JFETs Fabricated by Ion Implantation Into a High-Purity Semi-Insulating SiC Substrate

Silicon carbide (SiC) n-channel and p-channel junction field-effect transistors (JFETs) were fabricated by direct ion implantation into a high-purity semi-insulating 4H-SiC substrate toward complementary-JFET integrated circuit applications under a harsh environment. The fabricated n-JFET and p-JFET on a common substrate without an epitaxial layer show normal transistor operations up to 400 °C. Their electrical characteristics are comparable with theoretical estimations obtained from material parameters of n- and p-type SiC epitaxial layers. The present results assure that not only JFETs but also a variety of devices can be made by direct ion implantation while keeping material properties of epitaxially grown SiC.

D–T Neutron and 60Co-Gamma Irradiation Effects on HPSI 4H-SiC Photoconductors

The 14.1-MeV neutron irradiation- and 60Co-gamma irradiation-produced traps in high-purity semi-insulating (HPSI) 4H-SiC photoconductors (PCs) are reported, and the irradiation-induced changes in substrate resistivity, dark current, and UV response of the 4H-SiC PCs are analyzed. From the zero-bias thermally stimulated current measurements, six new traps at the energy levels $E_{v} \,+\, 0.58$ eV, $E_{v} \,+\, 0.68$ eV, $E_{v}\,+\, (0.7-0.9)$ eV, $E_{c} \, - \,0.64$ eV, $E_{c}\, -\, 0.91$ eV, and $E_{c} \, - \,1.04$ eV are identified in the 14.1-MeV neutron-irradiated PCs at the fluence of 1011 n/cm2, along the defects already detected before neutron irradiation. The thermal activation energy range (1–1.3 eV) for HPSI 4H-SiC is unaffected, and no considerable changes in the UV response of the PCs are noticed after the 14.1-MeV neutron irradiation. On the other hand, in addition to the traps determined prior to the irradiation, one new deep hole trap at $E_{v} + 1.31$ eV and significant changes in the activation energies (1.1–1.35 eV) are observed in the gamma-irradiated PCs at the dose of 100 Mrad, which suggest that the HPSI 4H-SiC substrate resistivity is increased due to the gamma irradiation-produced traps. Moreover, the signal-to-dark current ratio of the PCs is reduced after the gamma irradiation, as inferred from the UV response of the PCs.

Thermal Stability of Deep-Level Defects in High-Purity Semi-Insulating 4H-SiC Substrate Studied by Admittance Spectroscopy

Effects of high temperature treatments on the deep-level defects in high-purity semi-insulating substrates are studied by employing electrical and chemical analyses. Thermal admittance spectroscopy reveals the presence of a deep-level defect, labeled XMID, with a state near the middle of the bandgap, playing a decisive role to realize the semi-insulating characteristics. The concentration of the XMID level decreases with increasing treatment temperature from 1400 to 1700 °C, and consequently, the substrate becomes more conductive toward p-type due to residual boron impurities. The identity of XMID is yet to be known but the carbon vacancy is briefly discussed as a possible candidate.

High temperature annealing effects on deep-level defects in a high purity semi-insulating 4H-SiC substrate

Effects of high-temperature annealing on deep-level defects in a high-purity semi-insulating 4H silicon carbide substrate have been studied by employing current-voltage, capacitance-voltage, junction spectroscopy, and chemical impurity analysis measurements. Secondary ion mass spectrometry data reveal that the substrate contains boron with concentration in the mid 1015 cm−3 range, while other impurities including nitrogen, aluminum, titanium, vanadium and chromium are below their detection limits (typically ∼1014 cm−3). Schottky barrier diodes fabricated on substrates annealed at 1400–1700 °C exhibit metal/p-type semiconductor behavior with a current rectification of up to 8 orders of magnitude at bias voltages of ±3 V. With increasing annealing temperature, the series resistance of the Schottky barrier diodes decreases, and the net acceptor concentration in the substrates increases approaching the chemical boron content. Admittance spectroscopy results unveil the presence of shallow boron acceptors and deep-level defects with levels in lower half of the bandgap. After the 1400 °C annealing, the boron acceptor still remains strongly compensated at room temperature by deep donor-like levels located close to mid-gap. However, the latter decrease in concentration with increasing annealing temperature and after 1700 °C, the boron acceptor is essentially uncompensated. Hence, the deep donors are decisive for the semi-insulating properties of the substrates, and their thermal evolution limits the thermal budget for device processing. The origin of the deep donors is not well-established, but substantial evidence supporting an assignment to carbon vacancies is presented.

Plasma Etching of n-Type 4H-SiC for Photoconductive Semiconductor Switch Applications

Photoconductive semiconductor switches (PCSS) fabricated on high-purity semi-insulating 4H-SiC substrates (000\( \bar{1} \)) are capable of switching high currents in compact packages with long device lifetimes. A heavily doped n-type SiC epitaxial layer of appropriate thickness is required to form low-resistance ohmic contacts with these devices. In addition, to enhance the performance of the PCSSs, the SiC surface between the ohmic contacts must be extremely smooth. We report a chlorine-based, inductively coupled plasma reactive ion-etching process yielding n-type SiC epitaxial layers with the required smoothness. The rate of etching and post-etching surface morphology were dependent on plasma conditions. We found that the surface smoothness of epitaxial layers can be improved by including BCl3 in the argon–chlorine mixture. The optimum etching process yielded very smooth surfaces (∼0.3 nm RMS) at a relatively high rate of etching of ∼220 nm/min. This new fabrication approach significantly reduced the on-state resistance of the PCSS device and improved its durability of operation.

Fully Ion Implanted Vertical p-i-n Diodes on High Purity Semi-Insulating 4H-SiC Wafers

The fabrication of a fully ion-implanted and microwave annealed vertical p-i-n diode using high purity semi-insulating 4H-SiC substrate has been demonstrated for the first time. The thickness of the intrinsic region is the wafer thickness 350 µm. The anode and cathode of the diode have been doped with Al and P, respectively, to concentrations of few times 1020 cm-3 by ion implantation. The post implantation annealing has been performed by microwave heating the samples up to 2100°C. The device rectifying behavior indicates that a carrier modulation takes place in the bulk intrinsic region.

Fully implanted vertical p–i–n diodes using high-purity semi-insulating 4H–SiC wafers

The fabrication of a fully ion-implanted vertical p–i–n diode using high-purity semi-insulating 4H–SiC substrate has been demonstrated for the first time. The intrinsic region is the wafer itself with a thickness of 350 µm. The anode and cathode are obtained by doping the front and back wafer surfaces with implanted Al+ and P+ ions, respectively, with concentrations of about 1020 cm−3. The electrical activation of the implanted dopants is obtained by microwave heating the samples up to 2100 °C for 30 s. At ±100 V the on and off state current ratio is in the order of 104. Forward saturation current is five orders larger than it would be if controlled by the series resistance of the thick HPSI 4H–SiC intrinsic region.

Evaluation of Unintentionally Doped Impurities in Silicon Carbide Substrates Using Neutron Activation Analysis

Impurity atoms in a high-purity semi-insulating 4H-SiC substrate fabricated by sublimation and an n-type 3C-SiC substrate fabricated by Chemical Vapor Deposition (CVD) were evaluated by neutron activation analysis. Cr, Fe, Zn, As, Br, Mo, Sb, Eu, Yb, Hf, Ta, W and Au atoms were detected in the 4H-SiC fabricated by sublimation. In the 3C-SiC fabricated by CVD, Cr, Zn, As, Br, Mo, Sb, La Sm and Hf atoms were found. The concentration of these atoms tends to decrease with increasing atomic number.

Prominent defects in semi-insulating SiC substrates

Progresses in defects characterization of high-purity semi-insulating (HPSI) SiC substrates are reviewed. The vacancies, divacancy, and carbon vacancy–carbon antisite pairs were found to be dominating defects in HPSI 4H-SiC substrates with the thermal activation energy E a in the range ∼0.6–1.6 eV. Several vacancy-related deep acceptor levels were estimated and suggested to be responsible for the semi-insulating (SI) behavior in substrates with different E a. Deep levels associated with different activation energies are suggested. Annealing behavior of vacancy-related defects and the stability of the SI properties were studied. Prominent defects in SI 4H-SiC substrates doped with vanadium (V) were identified. Activation energies of E a∼1–1.1 eV were observed for V-doped samples with the V concentration ranging from 5.5×10 15 to 1.1×10 17 cm −3. Our results show that only in heavily V-doped samples, the activation energy E a∼1 eV is related to V, whereas in moderate V-doped materials, the SI properties are determined by intrinsic defects.

SiC MESFETs for High-Frequency Applications

AbstractSignificant progress has been made in the development of SiC metal semiconductor field-effect transistors (MESFETs) and monolithic microwave integrated-circuit (MMIC) power amplifiers for high-frequency power applications. Three-inch-diameter high-purity semi-insulating 4H-SiC substrates have been used in this development, enabling high-volume fabrication with improved performance by minimizing surface- and substrate-related trapping issues previously observed in MESFETs. These devices exhibit excellent reliability characteristics, with mean time to failure in excess of 500 h at a junction temperature of 410°C. A sampling of these devices has also been running for over 5000 h in an rf high-temperature operating-life test, with negligible changes in performance. High-power SiC MMIC amplifiers have also been demonstrated with excellent yield and repeatability. These MMIC amplifiers show power performance characteristics not previously available with conventional GaAs technology. These developments have led to the commercial availability of SiC rf power MESFETs and to the release of a foundry process for MMIC fabrication.

Thermally stimulated current spectroscopy of high-purity semi-insulating 4H-SiC substrates

High-purity semi-insulating (HPSI) 4H-SiC has been widely used as a substrate material for AlGaN/GaN high electron-mobility transistors because of its fairly good lattice match with GaN and its high thermal conductivity. To control material quality, it is important to understand the nature of the deep traps. For this purpose, we have successfully applied thermally stimulated current (TSC) spectroscopy to investigate deep traps in two HPSI 4H-SiC samples grown by physical vapor transport (PVT) and high-temperature chemical vapor deposition (HTCVD), respectively. Fundamentals of TSC spectroscopy, typical TSC spectra obtained on the two samples, and theoretical fittings of a boron-related trap (peaked at ∼ 150 K) will be presented. Based on literature data for deep traps in conductive 4H-SiC, the impurity and point-defect nature of several commonly observed TSC traps, peaked at ∼105 K (0.22 eV), ∼150 K (0.29 eV), ∼175 K (∼0.33 eV), ∼260 K (∼0.53 eV), ∼305 K (∼0.63 eV), and ∼360 K (0.91 eV), in the HPSI 4H-SiC will be discussed.

Photo-EPR and Hall Measurements on Undoped High Purity Semi-Insulating 4H-SiC Substrates

Photo-EPR and Hall Measurements on Undoped High Purity Semi-Insulating 4H-SiC Substrates