High Power Supply Ripple Rejection Research Articles

A 0.6V 44.6 ppm/ºC subthreshold CMOS voltage reference with wide temperature range and inherent leakage compensation

In this paper, a 0.6 V subthsheshold CMOS voltage reference (CVR) achieving wide temperature range and high power supply ripple rejection (PSRR) is presented. The proposed CVR structure can compensate the high temperature leakage and current mirror induced mismatches so as to increase the operating temperature range. The generated reference voltage of the proposed CVR circuit is the threshold voltage difference of two NMOS transistors, leading to relatively small variations. Moreover, the enhanced current source helps achieve high PSRR. The proposed CVR circuit is implemented in a standard 0.18-μm CMOS technology. Measurement results show that, with one single trimming, a mean output of 344 mV with standard deviation of only 2.89 mV and average TC of 44.6 ppm/°C over a wide temperature range from −40 °C to 125 °C is achieved. The measured PSRR is −68 dB, −52 dB and −52 dB at 10 Hz, 100 kHz and 10 MHz, respectively. The measured line sensitivity (LS) is 0.06%/V with a power supply from 0.6 V to 2 V while consuming 19.8 nW at 0.6 V supply. The active area is 0.019 mm2.

Design consideration in low dropout voltage regulator for batteryless power management unit

Harvesting energy from ambient Radio Frequency (RF) source is a great deal toward batteryless Internet of Thing (IoT) System on Chip (SoC) application as green technology has become a future interest. However, the harvested energy is unregulated thus it is highly susceptible to noise and cannot be used efficiently. Therefore, a dedicated low noise and high Power Supply Ripple Rejection (PSRR) of Low Dropout (LDO) voltage regulator are needed in the later stages of system development to supply the desired load voltage. Detailed analysis of the noise and PSRR of an LDO is not sufficient. This work presents a design of LDO to generate a regulated output voltage of 1.8V from 3.3V input supply targeted for 120mA load application. The performance of LDO is evaluated and analyzed. The PSRR and noise in LDO have been investigated by applying a low-pass filter. The proposed design achieves the design specification through the simulation results by obtaining 90.85dB of open-loop gain, 76.39º of phase margin and 63.46dB of PSRR respectively. The post-layout simulation shows degradation of gain and maximum load current due to parasitic issue. The measurement of maximum load regulation is dropped to 96mA compared 140mA from post-layout. The proposed LDO is designed using 180nm Silterra CMOS process technology.

A −80 dB PSRR 4.99 ​ppm/°C TC bandgap reference with nonlinear compensation

A precision bandgap reference (BGR) with high power supply ripple rejection (PSRR) and low temperature coefficient (TC) is proposed for the peripheral compensation circuitry of active-matrix organic light-emitting diode (AMOLED) displays. The PSRR is enhanced by a coupling structure of the power supply and a feedback loop of the start-up circuit. Furthermore, a high-order nonlinear compensation method is proposed to reduce the temperature coefficient by utilizing the systematic nonlinear offset voltage within the bandgap circuit. Measurement results of the proposed BGR implemented in an industrial 0.25-μm CMOS process demonstrate a TC of 4.99 ​ppm/°C in a wide temperature range of −40 ​°C–130 ​°C. A PSRR around −80 dB is also achieved by the proposed circuit at low frequency.

A 0.9-V 33.7-ppm/°C 85-nW Sub-Bandgap Voltage Reference Consisting of Subthreshold MOSFETs and Single BJT

A low temperature coefficient (TC) and high power supply ripple rejection (PSRR) CMOS sub-bandgap voltage reference (sub-BGR) circuit using subthreshold MOS transistors and a single BJT is presented in this brief. The proposed sub-BGR consists of a novel complementary-to-absolute-temperature (CTAT) voltage generator based on a scaled emitter-base voltage of a BJT, and an improved proportional-to-absolute-temperature (PTAT) voltage generator based on stacking of $\Delta V_{\mathbf {GS}}$ of sub- $V_{\mathbf {TH}}$ MOSFETs. As the CTAT circuit achieves a reduced absolute value of the negative TC, the PTAT circuit achieves reduced power consumption without consuming a large chip area. The proposed sub-BGR circuit is implemented in a standard 0.18- $\mu \text{m}$ CMOS process. Measured results show that the sub-BGR circuit can run with a supply voltage down to 0.9 V while the power consumption is only 85 nW. An average TC of 33.7 ppm/°C and a PSRR of better than −40 dB over the full frequency range are achieved.

A 0.6-V Minimum-Supply, 23.5 ppm/°C Subthreshold CMOS Voltage Reference With 0.45% Variation Coefficient

In this brief, a low-voltage low-temperature- coefficient (TC) subthreshold CMOS voltage reference (CVR) is presented. The proposed CVR employs the ${\Delta }\text{V}_{\mathbf{GS}}$ of different-threshold and same-threshold nMOS transistor pairs to generate the complementary-to-absolute-temperature and proportional-to-absolute-temperature voltages, respectively. Low TC with small variations and high power supply ripple rejection (PSRR) are achieved. The proposed design is fabricated in a standard 0.18- $ {\mu }\text{m}$ CMOS process. It measures an average reference voltage of 218.3 mV with a deviation of 0.97 mV and variation coefficient of 0.45%. It achieves an average TC of 23.5 ppm/°C for a temperature range of −40 °C to 125 °C. The measured PSRR is −66.4 dB, −42.4 dB and −42.3 dB at 10 Hz, 1 kHz and 10 MHz, respectively. The measured line sensitivity is 0.40%/V for 0.6 V to 2.0 V supply. The consumed power is 30.5 nW at 0.6-V supply.

Analysis and design of a current-mode bandgap reference with high power supply ripple rejection

In this paper, a current-mode bandgap reference (BGR) circuit with cascode current mirrors and improved frequency compensation for achieving high power supply ripple rejection (PSRR) is presented. By slightly modifying a conventional frequency compensation scheme, the PSRR of the BGR is significantly enhanced. PSRRs of the BGR with the two different compensation techniques have been formulated and verified. Moreover, design considerations are presented, taking into account the critical parasitic capacitor's effect in PSRR. To our knowledge, this is the first time in the literature of explicitly demonstrating how the PSRR of a BGR is improved due to the frequency compensation. The feedback loop stability is also analyzed. The measured PSRR of an example BGR using the modified compensation fabricated in a standard 0.18-μm CMOS process is −77dB and −62dB at 1kHz, and 100kHz, respectively, with more than 40dB improvement at the high frequency ranges over the design with the classical compensation.

An amplifier‐offset‐insensitive and high PSRR subthreshold CMOS voltage reference

SummaryAn amplifier‐offset‐insensitive complementary metal‐oxide‐semiconductor (MOS) voltage reference (CVR) circuit with high power supply ripple rejection (PSRR) is presented. Due to the novel structure of employing subthreshold MOS transistors, the proposed CVR circuit can suppress the direct current offset effects of the internal amplifier. Design considerations in optimizing the power and area consumptions and improving the PSRR are presented. The proposed CVR circuit is implemented in a standard 0.18 μm complementary MOS process. Measured results show that the reference can run with down‐to 0.9 V supply voltage, while the power consumption is only 70 nW. The measured PSRR is better than −37 dB over the full frequency range.