High-performance Phase-locked Loop Research Articles

Field trial of stable radio frequency transfer system in 200 km metropolitan optical fiber link.

In this paper, we demonstrate stable radio frequency (RF) transfer via metropolitan optical fiber link in the Beijing area. The phase variation of the RF signal is compensated by a phase conjugation method incorporating two high-performance phase-locked loops. The wavelength conversion module extends the transmission length to 200 km with only two parallel 50 km dark optical fibers available. We optimize the configuration of dispersion compensation and optical amplification due to the high loss (0.31 dB/km) of the optical fiber link. At the same time, comparative experiments verify the short-term instability limitation that arises from the group velocity dispersion of the optical fiber link. The measured standard Allan deviation of the 2.4GHz RF transmission system with dispersion compensation is 4.5 × 10-14/1 and 2.6 × 10-17/20 000s, which is superior to that of the reference rubidium clock. The short-term instability of the system is deteriorated to 2.5 × 10-13/1s without dispersion compensation.

A Novel Bias Circuit Technique to Reduce the PVT Variation of the Ring Oscillator Frequency

Phase Locked Loop (PLL) is an on-chip clock generator for timing-centric electronic systems. Voltage Controlled Oscillator (VCO) is the key element for high-performance PLLs. A detailed qualitative explanation has been given to describe VCO operation. It is shown from simulation results that the variation of small signal transconductance ([Formula: see text]) is the main dominant source of frequency and gain ([Formula: see text]) variation in a VCO. In this work, simulation results for the conventional ring oscillator are presented which demonstrates [Formula: see text] times variation in [Formula: see text] across Process Voltage Temperature (PVT) corners. Such huge sensitivity to PVT is undesirable for high bandwidth PLL design. To mitigate this sensitivity, a constant-gm bias circuit is proposed in this paper, with a detailed mathematical analysis. A prototype of 4-stage ring oscillator with center frequency of 5[Formula: see text]GHz is developed in 65[Formula: see text]nm TSMC CMOS technology, and post-layout simulation results are carried out. Results show that maximum [Formula: see text] variation of 28% and frequency variation of 17% at a given control voltage. Temperature sensitivity has been decreased from 19.3% to 7% using the proposed biasing technique. Proposed solution consumes 2.4[Formula: see text]mW power from 1[Formula: see text]V power supply.

A High-Performance Pll Observer for Sensorless Three-Phase Induction Motor Control

This paper presents an enhanced estimation algorithm based on the PLL (phase-locked loop) approach, which is used to estimate the rotor speed in induction motors (IM) drives. It can be challenging to obtain an accurate estimate during frequency ramps using existing PLL schemes. Thus, the performance of PLL schemes can be degraded during the acceleration and deceleration operations when applied to motor drives. In addition, the performance of conventional PLL scheme estimation is negatively affected by disturbances, for example, DC offsets. One of the novelties of the proposed speed observer (HPPO - High-Performance PLL Observer) is error normalization, which is based on the currents and a mechanism of variable gain based on the reference speed. The reference speed is also used to build an additional feedforward adjustment action. These modifications improve estimator results during load insertions and at low rates. In order to validate the proposed HPPO algorithm, it is implemented experimentally in a laboratory prototype using a 2.2kW IM. The motor is driven by a three-phase pulse width modulation (PWM) power converter, which is controlled by a DSP TMS320F28069. Numerical analysis and experimental results are carried out to validate the proposed scheme's high performance.

Trends and New Opportunities in Digital Phase-Locked Loop Design: Design Principles, Key Overheads, and New Opportunities in This Emerging Architecture

Phase-locked loop (PLL)-based frequency synthesizers are pervasively utilized in almost every electronic system for generating welldefined clock frequencies of interest. For instance, in a modern wireless transceiver, a radio-frequency (RF) synthesizer is typically used as a local oscillator to upconvert/downconvert the desired signal to and from the proper communication bands. A similar utilization of RF PLL can be seen in a wireline transceiver, which modulates and demodulates the data symbol at a precise frequency and phase. In addition to RF applications, PLL is also commonly used in baseband and digital circuitry, such as generating a sampling clock for switched-capacitor circuits and clocking the sequential logic of the digital circuitry. As the complexity of the modern system-onchip (SoC) platform continues to grow, it is likely to require numerous highperformance PLLs. Moreover, interference coupling through the same silicon substrate is exacerbated. As a result, the low implementation (area and power) cost, high reconfigurability, resilience over interferences, and reduced design time of a PLL have become increasingly important in light of this new trend.

Ultrastable Long-Haul Fiber-Optic Radio Frequency Transfer Based on Dual-PLL

In this paper, we demonstrate ultrastable radio-frequency (RF) transfer over long-haul optical fiber link. Our stabilized RF transfer technique is based on high-performance dual phase locked loops (dual-PLL) configuration which improves signal to noise ratio (SNR) of the round trip transmitted signals. At the local site, the frequency conversion phase-lock receiver (FCPLR) accomplishes high-quality phase tracking of the RF signal which is transmitted after long distance optical fiber link. The low phase noise signal generated by FCPLR is passively mixed with a local reference signal to realize phase conjugation. Through advisable frequency design, there is no residual RF leakage and nonlinear effect of frequency mixing. Another PLL incorporating a high-quality cleanup oscillator is located at the remote site that favourably improves short-term instability of our transmission system. In our experiment, stabilized 2.4 GHz RF signal transfer over a 1007 km optical fiber link is demonstrated without any electric relay system, and the transmission system achieves a fractional frequency instability of 8.20 × 10 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">-14</sup> @1 sand 7.87 × 10 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">-17</sup> @10 000 s.

Design of a High Performance Phase-Locked Loop With DC Offset Rejection Capability Under Adverse Grid Condition

In the new energy grid-connected power generation system, accurately extracting the grid synchronization signals such as the frequency, phase and amplitude of the grid voltage is the basis for effective control. Aiming at the requirements for detecting grid synchronization signals under unbalanced, harmonics and DC offset voltage mixed conditions, a dual second-order complex coefficient filter with DC offset rejection capability (DSOCCF <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">dc</sub> ) is proposed, combining the approach of moving average filter (MAF), a novel hybrid filter in dq-frame is designed and on the basis of this design a new synchronous reference frame phase locked loop (SRF-PLL) design approach based on the hybrid filter is proposed. The proposed approach employs moving average filter (MAF) to block the high-frequency harmonics in the grid voltage, and uses DSOCCF <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">dc</sub> to separate the fundamental frequency positive and negative sequence and reject DC offset. It can accurately extract the synchronization information of the grid fundamental frequency positive sequence. After simulation and experiment verification, it can be confirmed that the proposed PLL can quickly and accurately lock the properties of the grid voltage under adverse grid condition, and also have high detection accuracy and strong robustness to frequency fluctuations.

High performance PLL for multiband GSM applications

Dead zone very often poses to be a limitation in the high performance phase locked loops (PLLs). The design of a dead zone free PLL with fast locking and low phase noise capability is proposed. This is achieved by using a voltage variable delay element (VVDE) in the feedback path or reset path of the phase frequency detector (PFD). A feedback from one of the inputs of charge pump circuit is used to retain the overall PFD delay slightly positive to escape dead zone at lesser phase noise. The PLL performance with this proposed PFD is analysed in the cadence design environment. It attains phase noise of –110.5 dBc/Hz at 1 MHz offset frequency which is superior as compared to the other two reported techniques. Achieving this superior phase noise performance the PLL consumes lesser power of 2.56 mW at the cost of 5% extra physical area. This performance is also compared with that of PLL where no delay and fixed delay element is used to reduce the dead zone.

Single-Phase Phase-Locked Loop Based on Derivative Elements

High-performance phase-locked loops (PLLs) are critical for power control in grid-connected systems. This paper presents a new method of designing a PLL for single-phase systems based on derivative elements (DEs). The quadrature signal generator (QSG) is constructed by two DEs with the same parameters. The PLL itself is realized by using the DE-based QSG. It avoids errors due to the overlap and accumulation that are present in PLLs based on integral elements, such as a PLL based on a second-order generalized integrator. Additionally, frequency feedback is not needed which allows the proposed PLL to achieve high performance when the grid frequency changes rapidly. This paper presents the model of the PLL and a theoretical performance analysis with respect to both the frequency-domain and time-domain behavior. The error arising from the discretization process is also compensated, ensuring this PLL method is suitable for implementation in a digital control system. Simulation and experimental results show that the proposed PLL achieves good performance in both harmonic rejection and dynamic response.

A Novel PLL Resolver Angle Position Indicator

This paper describes a novel and high-performance phase-locked loop (PLL) resolver converter for the measurement of mechanical angles. The proposed method does not require the use of demodulators, voltage-controlled oscillator, digital-to-analog converter, counter, and lookup tables, that are associated with conventional PLL converters. The proposed method employs full-wave rectifiers to obtain the absolute values of the modulated resolver signals. This scheme results in a triangular output voltage and two binary outputs that represent a measure of the input angle. The required sine and cosine of the estimated angle, which are needed for PLL converters, are determined using simple approximation techniques. The proposed method can be used to measure angles in the full 360° range, is simpler than the available techniques, and may be easily implemented using digital or basic analog electronic circuitry. This paper describes the proposed method, full details of its implementation using standard electronic components, and experimental results. The performance of the proposed converter is comparable with that of a commercial product.

Costas Loop Homodyne Detection for 20-Gb/s QPSK Signal on the Optical Frequency Synchronous Network

This paper demonstrates a decision-directed, stable and high-sensitivity Costas loop homodyne receiver for 20-Gb/s QPSK signals based on our concept of the “optical frequency synchronous network.” The receiver sensitivity is shown to approach the theoretical shot-noise limit (as degraded by spontaneous emission) and the symbol-error rate is stably measured to be around 10−3 even though the optical signal was chirped by fiber chromatic dispersion and was delayed by 50% of the symbol period. This high-performance phase-locked loop can be realized by utilizing optical frequency stabilized (synchronized) several kilohertz spectral line-width external cavity laser diodes (E-LD's), compensating the frequency modulation (FM) response of the E-LDs, and consisting of only differential mode logical circuits. The compensation of the E-LD's FM response by the loop filter improves the receiver sensitivity by 3 dB.

Two-stage feedback-looped charge-pump for spur reduction in CMOS PLL

In this paper, two-stage charge pump is proposed for high performance phase-locked loop (PLL). Two-stage charge pump is to minimize the current mismatch and keeps the constant current across a wide range of output voltage. The charge pump is composed of the two-stage circuit which has the conventional push---pull charge pump and the compensation circuit. The compensation circuit has a feedback biasing circuit and an op-amp to act as a voltage follower. The proposed charge pump is applied in 2 GHz analog PLL to check out the noise spectrum of the spur and phase offset which are occurred from the current mismatch. PLL is designed with 0.18-µm CMOS process. In the post-layout simulation, the proposed charge pump indicates that the current mismatch is less than 5 % over the voltage range of 0.25---1.45 V which covers almost 70 % of the 1.8 V supply voltage. The spur in PLL is obtained to be ?63.7 dBc with the power consumption of 13 mW.

A High-Performance PLL With a Low-Power Active Switched-Capacitor Loop Filter

A 2.5-GHz phase-locked loop (PLL) employing a low-power active switched-capacitor loop filter is presented. A subthreshold inverter-based active loop filter is presented and analyzed. Advantages such as type-II loop dynamics, low reference spurs, and small on-chip capacitors are achieved. In addition, 1/f noise of the inverter amplifier can be suppressed by the filter's auto-zeroing operation. The prototype is designed and fabricated in a 0.18- μm CMOS technology. Measurement results show phase noise of -86 dBc/Hz at a 100-kHz offset, -124.0 dBc/Hz at a 3-MHz offset, and a reference spur level of -64 dBc. The PLL consumes about 16 mW with 0.46 mW dedicated to the loop filter active components.

Time-based frequency band selection method for phase-locked loops

High-performance phase-locked loops (PLLs) often require voltage-controlled oscillators (VCOs) employing both discrete and continuous tuning mechanisms to satisfy a wide frequency range and a low VCO tuning gain simultaneously. An auxiliary circuit is required to facilitate the selection among a group of discrete bands. An agile technique to search for an optimum VCO frequency band is proposed. The search is based on measuring the period difference between a reference and the VCO-divided signals. The VCO band selection circuit is implemented with a 10 GHz PLL in a 0.18 µm CMOS process and consumes only an extra 3 mA. The band selection time is less than 4 µs.