High-performance Packet Switch Research Articles

A QoS-Aware Dual Crosspoint Queued Switch with Largest Weighted Occupancy First Scheduling Algorithm

Support of incoming traffic differentiation and Quality of Service (QoS) assurance is very important for the development of high performance packet switches, capable of separating traffic flows. In our previous paper, we proposed the implementation of two buffers at each crosspoint of a crossbar fabric that leads to the Dual Crosspoint Queued (DCQ) switch. Inside DCQ switch, one buffer is used to store the real-time traffic and the other for the non-real-time traffic. We also showed that the static priority algorithms can provide the QoS only for the real-time traffic due to their greedy nature that gives the absolute priority to that type of traffic. In order to overcome this problem, in our paper we propose the DCQ switch with the Largest Weighted Occupancy First scheduling algorithm that provides the desired QoS support for both traffic flows. Detailed analysis of the simulation results confirms the validity of proposed solution.

Power and Delay Aware Management of Packet Switches

Due to increasing circuit densities and data throughput rates, power consumption has become a significant concern in the design and operation of high-performance packet switches. We extend the idea of Dynamic Power Management (DPM) to input queued switches, allowing operators to tradeoff power and delay in a useful way. We frame the problem as a dynamic program and solve a relaxation using techniques from Linear Quadratic Regulation (LQR). This optimal policy is combined with existing, nonpower-aware switch controls to generate two novel scheduling algorithms: 1) LQR Power Aware Maximum Weight Matching (LQR PA MWM) and 2) LQR Power Aware Projective Cone Scheduling (LQR PA PCS). Simulation results suggest that our algorithms result in significant power savings compared to MWM and previous power control schemes with little performance degradation.

A Simulation-Based Comparison of Multimedia Traffic Prioritization Schemes for High-Performance Input-Queued Packet Switches

This study investigates the problem of enabling Quality of Service (QoS) of multimedia traffic at the input port of high-performance input-queued packet switches using a simulation-based evaluation. We focus on the possibility of assuring QoS of multimedia traffic in such switches by implementing traffic prioritization at the input port where each input-queue has been modified to provide a separate buffer for each of the service classes. The multimedia traffic can be categorized into three classes based on its real-time properties and loss tolerance and assigned a separate queue for each class. We select appropriate models for each of three types of traffic: video, voice and data. Then, we propose an efficient dynamic scheduling strategy by implementing multimedia traffic prioritization at the input port of input-queued packet switches. Simulation-based comparisons show that while the static priority scheme is beneficial for highest priority class at the expense of the others, the dynamic prioritization serves fairly well all the classes in terms of delay and loss requirements.

A Cell Selection Policy For An Input-Buffered Packet Switch

The literature contains many theoretical solutions to the design of high-performance packet switches, related to buffering, selection, and routing functionalities. Different selection policies and scheduling algorithms providing 100% throughput, such as MSM, MWM, and the like, have been proposed. However, in practice many of them introduce a high complexity and are not feasible. In this paper, we suggest a simple cell selection policy implemented by hardware for an input-queuing architecture using a multistage interconnection network. The proposal is described and simulated using a VHDL language. Performances in terms of delay, throughput, and cell loss are evaluated.

High-performance adaptive routing for networks with arbitrary topology

A strategy to implement adaptive routing in irregular networks is presented and analyzed in this work. A simple and widely applicable deadlock avoidance method, applied to a ring embedded in the network topology, constitutes the basis of this high-performance packet switching. This adaptive router improves the network capabilities by allocating more resources to the fastest and most used virtual network, thus narrowing the performance gap with regular topologies. A thorough simulation process, which obtains statistically reliable measurements of irregular network behavior, has been carried out to evaluate it and compare with other state-of-the-art techniques. In all the experiments, our router exhibited the best behavior in terms of maximum/sustained performance and sensitivity to the network topology.

A Novel Algorithm for Maintaining Packet Order in Two-Stage Switches

To enhance the scalability of high performance packet switches, a two-stage load-balanced switch has recently been introduced, in which each stage uses a deterministic sequence of configurations. The switch is simple to make scalable and has been proven to provide 100% throughput. However, the load-balanced switch may mis- sequence the packets. In this paper, we propose an algorithm called full frame stuff (FFS), which maintains packet order in the two-stage load-balanced switch and has excellent switching performance. This algorithm is distributed and each port can operate independently.

An evolutionary management scheme in high-performance packet switches

This paper deals with a novel buffer management scheme based on the combination of evolutionary computing and fuzzy logic for shared-memory packet switches. The philosophy behind it is adaptation of the threshold for each logical output queue to the real traffic conditions by means of a system of fuzzy inferences. The optimal fuzzy system is achieved using a systematic methodology based on Genetic Algorithms for membership-function selecting and tuning. This methodology approach allows the fuzzy system parameters to be automatically derived when the switch parameters vary, offering a high degree of scalability to the fuzzy control system. Its performance is close to that of the push-out mechanism, which can be considered ideal from a performance viewpoint, and at any rate much better than that of threshold schemes based on conventional logic. In addition, the fuzzy threshold scheme is simple to implement, unlike the push-out mechanism which is not practically feasible in high-speed switches due to the amount of time required for computation, and above all inexpensive when implemented using current standard technology.

An SFQ-based high-performance packet switch for next-generation high-end routers

Switching throughput capacities of over 10 Tbps will be required of high-end systems on the backbones of nationwide telecommunications networks within the next decade. However conventional technologies cannot accommodate such capacities. Superconducting single flux quantum (SFQ) technology is a promising approach because of its ultra-low power consumption and ultra-high speed characteristics. We have proposed an opto-electronic-SFQ hybrid switching system. This system is separated into three functions: SFQ packet switching, high-performance CMOS control, and optical transmission. The packet switch is an improved Batcher–Banyan switch that uses a time-shifted internal speedup unit, and shuffle and grouping exchange schemes. Simulation showed good scalability; no conventional router could ever attain this capacity. We report on the numerical analysis and architectural-level design results for this packet switch.

Derivation of the mean cell delay and cell loss probability for multiple input-queued switches

The multiple input-queued (MIQ) asynchronous transfer mode (ATM) switch has drawn much interest as a promising candidate for a high-speed and high-performance packet switch. The most conspicuous feature of the switch is that each input port is equipped with m(1/spl les/m/spl les/N) distinct queues, each for a group of output ports. Since the MIQ switch has multiple queues, an input can serve up to m cells in a time slot, leading to an enhanced performance. We derive the average queue length, mean cell delay, and cell loss probability for the MIQ switch in terms of the number of queues in an input port (m) and input load. The results include a special case of the single input-queued (SIQ) switch (m=1), which is analyzed by Hui et al. (1987).

RAZAN: a high-performance switch architecture for ATM networks

In this paper a high-performance packet switch architecture based on the improved logical neighbourhood (ILN) interconnection network, called RAZAN, is presented. RAZAN is an N × N multistage interconnection network (MIN) which consists of n stages, where n = log2N, of switching elements. Each stage consists of a column of N switching elements and (n + 1) × N links. Each switch has n + 1 inputs and n + 1 outputs. Every switching element j is connected to those n + 1 neighbouring switches in the next stage whose binary addresses differ by at most 1 bit from the binary address of switch j. The performance of RAZAN is evaluated both analytically and via simulation under uniform traffic load. The analytical and simulation performance evaluation results are compared. The performance of RAZAN is compared with a number of existing ATM switch architectures such as Benes, parallel banyan and Tagle networks. It is shown that RAZAN exhibits better performance in terms of both the rate of cell loss and throughput. This advantage of RAZAN over existing ATM switch architectures has been achieved at the expense of a moderate increase in switch complexity. In addition, an important characteristic which RAZAN possesses and which distinguishes it further from most existing ATM switch architectures is its ability to achieve very high throughput (higher than 80 per cent) in the presence of faulty switches and/or links. In this paper the fault tolerance characteristics of RAZAN are presented. However, space constraints do not allow us to present a detailed analysis of the fault tolerance and reliability features of RAZAN. These aspects are elaborated in a separate publication. © 1998 John Wiley & Sons, Ltd.

SXmin: a self-routing high-performance ATM packet switch based on group-knockout principle

We propose SXmin: a self-routing, group-knockout principle based asynchronous transfer mode (ATM) packet switch which provides comparable delay-throughput performance and packet loss probabilities at significantly reduced hardware requirements compared to earlier switches. The M/spl times/N SXmin consists of an N/spl times/N Batcher sorter followed by log/sub 2/N-1 stages of sort-expander (SX) modules arranged in the form of a complete binary tree. Each SX module consists of a column of 2/spl times/2 switches with a wraparound-unshuffle input-output interconnection. This enables the hierarchical utilization of the group-knockout principle to expand the number of inputs by a small factor at each stage, resulting in a significant reduction in overall hardware complexity. Routing at each switch is controlled by a single bit. However, in case of contention, a dual bit resolution algorithm is used locally which drops excess packets in a predetermined manner while ensuring global randomness of packet loss over the entire switching network. There are no internal buffers at the individual stages and therefore the internal delay is constant and proportional to the number of stages. The use of simple hardware components and regular interconnections in the SX modules makes the network suitable for optical implementation.

A multiservice high-performance packet switch for broad-band networks

An input queued packet switch for broadband networks that supports data link connections and whose capacity is not constrained by the capacity of a single packet channel is described. The switch bandwidth is allocated at two different times. At connection setup time, an output data link (a channel group) is selected on which some bandwidth is reserved for the new call. At transmission time, specific channels within the data link are optimally allocated, slot by slot, to the packets addressed to that link, solving the output channel contention at the same time. The interconnection network of the switching is basically a Batcher-banyan network including the additional networks required to handle channel groups and to allocate bandwidth fairly at transmission time. Packet sequence integrity can be guaranteed for jitter-sensitive services, as the emulation of a circuit connection. It is shown that the channel group capability of the switch greatly improves the performance of standard input queued packet switches, so that input queuing with suitable data link capacities and output queueing give comparable performances.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

Queueing in high-performance packet switching

The authors study the performance of four different approaches for providing the queuing necessary to smooth fluctuations in packet arrivals to a high-performance packet switch. They are (1) input queuing, where a separate buffer is provided at each input to the switch; (2) input smoothing, where a frame of b packets is stored at each of the input line to the switch and simultaneously launched into a switch fabric of size Nb*Nb; (3) output queuing, where packets are queued in a separate first-in first-out (FIFO) buffer located at each output of the switch; and (4) completely shared buffering, where all queuing is done at the outputs and all buffers are completely shared among all the output lines. Input queues saturate at an offered load that depends on the service policy and the number of inputs N, but is approximately 0.586 with FIFO buffers when N is large. Output queuing and completely shared buffering both achieve the optimal throughput-delay performance for any packet switch. However, compared to output queuing, completely shared buffering requires less buffer memory at the expense of an increase in switch fabric size.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

Design of a broadcast packet switching network

An overview is given of a system designed to handle a heterogeneous and dynamically changing mix of applications. It is based on fiber-optic transmission systems and high-performance packet switching and can handle applications ranging from low-speed data to voice to full-rate video. A novel feature is a flexible multipoint connection capability suitable for broadcast and conferencing applications. The architecture of a switching systems that can be used to support this network is described. >

A photonic knockout switch for high-speed packet networks

A high-performance packet switch is discussed which uses a photonic interconnect fabric to route very-wideband data packets from input to output. Packet contention is accomplished using a much slower electronic controller, based on the knockout principle operating in parallel with the optical interconnect. Specifically, the use of a wavelength-division-multiplex fabric whereby high-speed (2-4 Gb/s) packets are regenerated before modulating a single-frequency laser at each switch input. The optical signals from various inputs are summed in a star coupler and then broadcast to the different coupler outputs. Each coupler is equipped with a small number (L) of tunable receivers arranged in a parallel manner, each preceded by a power splitter so that up to L simultaneous packets can be received by each output. The L packets so received are stored in an L-input one-output first-in first-out (FIFO) buffer so that the FIFO packet sequence is always guaranteed. Not only does this architecture achieve the best delay-throughput performance, but, remarkably, modularity is such that the optical complexity grows linearly with the number of switch ports./.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>