High-performance Implementation Research Articles

ON THE DESIGN AND FABRICATION OF CHAINED-FUNCTION WAVEGUIDE FILTERS WITH REDUCED FABRICATION SENSITIVITY USING CNC AND DMLS

In this paper, we present the design and fabrication of a novel class of emerging waveguide filters based on chained-functions at the millimeter-wave band. The derivation of chained-functions by chaining of prescribed generalized Chebyshev seed functions based on the partition theory is presented in details, and the implementation to waveguide technology is proposed and evaluated. The waveguide filter is fabricated through two different technologies, namely the Computer Numerical Control (CNC) milling technology and the Direct Metal Laser Sintering (DMLS) based additive manufacturing technology. The chained-function filters, which lie in between the Butterworth and Chebyshev filters, inherit the salient properties of both Butterworth and Chebyshev filters. Therefore, the chained-function waveguide filter exhibits filtering responses that have a superior rejection property and a lower loss with reduced sensitivity to fabrication tolerance than the standard Chebyshev waveguide filter. The efficiency of the proposed waveguide filter is confirmed both theoretically and empirically, using the CNC and DMLS processes. The issues of a higher manufacturing tolerance and apparent surface roughness associated with the DMLS method are found to be electrically insignificant when the chained-function concept is adopted in waveguide filter design. In general, the measured results of all the realized waveguide filters agree well to those of the simulation models. These results positively demonstrate that the chainedfunction concept has robust properties for rapid, high-performance, low-cost, and sustainable filter design and implementation, particularly for higher millimeter-wave frequency bands and for narrowband applications. © 2020.

High-Performance Implementation of Dynamically Configurable Load Balancing Engine on FPGA

Load balancing technology plays an important role in task distribution. At present, mainstream solutions are implemented by software, and the delay introduced is longer; others implemented by hardware do not achieve excellent performance. This article proposes an implementation scheme of a reconfigurable load balancing engine on an FPGA. This engine could distribute network packets to CPU cores over a five-tuple, and the delay brought by balancing algorithm is only about 26 ns. Furthermore, this engine can process all frame sizes of packets at 100 percent line rate and zero packet loss rate, achieving excellent performance. At the same time, this engine supports dynamic configuration and can be set flexibly according to different scenarios.

A bounded numerical solver for a fractional FitzHugh–Nagumo equation and its high-performance implementation

In this paper, we propose a high-performance implementation of a space-fractional FitzHugh–Nagumo model. Our implementation is based on a positivity- and boundedness-preserving finite-difference model to approximate the solutions of a Riesz space-fractional reaction-diffusion equation. The model generalizes the FitzHugh–Nagumo model. The stability and convergence of the difference scheme are thoroughly discussed. Moreover, we prove the existence and uniqueness of numerical solutions, positivity, boundedness and consistency of the model. The scheme is based on weighted and shifted Grunwald differences. The conjugate gradient method is used then to solve the sparse matrix system. The MPI and PETSc libraries are used for the computational implementation. We investigate the influence of some computer factors on the performance of our implementation and scalability. More precisely, we consider the number of cores, the size of the computation mesh and the orders of the fractional derivatives. Tests are evaluated on a ccNUMA architecture with two CPUs.

Algorithmic and language-based optimization of Marsa-LFIB4 pseudorandom number generator using OpenMP, OpenACC and CUDA

The aim of this paper is to present new high-performance implementations of Marsa-LFIB4 which is an example of high-quality multiple recursive pseudorandom number generators. We propose an algorithmic approach that combines language-based vectorization techniques together with a new divide-and-conquer parallel method that exploits a special sparse structure of the matrix obtained from the recursive formula that defines the generator. Our portable OpenACC implementation achieves the performance comparable to those achieved by our CUDA-based and OpenMP-based implementations on GPUs and multicore CPUs, respectively.

A surrogate ℓ0 sparse Cox's regression with applications to sparse high-dimensional massive sample size time-to-event data.

Sparse high-dimensional massive sample size (sHDMSS) time-to-event data present multiple challenges to quantitative researchers as most current sparse survival regression methods and software will grind to a halt and become practically inoperable. This paper develops a scalable ℓ0 -based sparse Cox regression tool for right-censored time-to-event data that easily takes advantage of existing high performance implementation of ℓ2 -penalized regression method for sHDMSS time-to-event data. Specifically, we extend the ℓ0 -based broken adaptive ridge (BAR) methodology to the Cox model, which involves repeatedly performing reweighted ℓ2 -penalized regression. We rigorously show that the resulting estimator for the Cox model is selection consistent, oracle for parameter estimation, and has a grouping property for highly correlated covariates. Furthermore, we implement our BAR method in an R package for sHDMSS time-to-event data by leveraging existing efficient algorithms for massive ℓ2 -penalized Cox regression. We evaluate the BAR Cox regression method by extensive simulations and illustrate its application on an sHDMSS time-to-event data from the National Trauma Data Bank with hundreds of thousands of observations and tens of thousands sparsely represented covariates.

Design and Control of a GaN-Based, 13-Level, Flying Capacitor Multilevel Inverter

Multilevel topologies are an appealing method to achieve higher power density converters for both mobile and stationary systems. This article discusses the design and high-performance hardware implementation of a 13-level, flying capacitor multilevel (FCML) inverter. Derivation of flying capacitor sizing for ac output voltages (for an arbitrary level FCML) is provided. Operating from an 800- $V_{\text {dc}}$ bus, this hardware prototype utilizes switch modules with 100-V rating. Moreover, a 120-kHz switching frequency is enabled through the use of gallium nitride (GaN) FETs and the development of custom-integrated switching cells, which reduce commutation loop inductance and allow for a modular design. The frequency multiplication effect of FCML inverters allows the output inductor of the inverter to be made exceptionally small ( $4.7~\mu \text{H}$ ) while maintaining a 0.7% total harmonic distortion (THD) due to the 1.44-MHz effective inductor ripple frequency.

The chemfp project

The chemfp project has had four main goals: (1) promote the FPS format as a text-based exchange format for dense binary cheminformatics fingerprints, (2) develop a high-performance implementation of the BitBound algorithm that could be used as an effective baseline to benchmark new similarity search implementations, (3) experiment with funding a pure open source software project through commercial sales, and (4) publish the results and lessons learned as a guide for future implementors. The FPS format has had only minor success, though it did influence development of the FPB binary format, which is faster to load but more complex. Both are summarized. The chemfp benchmark and the no-cost/open source version of chemfp are proposed as a reference baseline to evaluate the effectiveness of other similarity search tools. They are used to evaluate the faster commercial version of chemfp, which can test 130 million 1024-bit fingerprint Tanimotos per second on a single core of a standard x86-64 server machine. When combined with the BitBound algorithm, a k = 1000 nearest-neighbor search of the 1.8 million 2048-bit Morgan fingerprints of ChEMBL 24 averages 27 ms/query. The same search of 970 million PubChem fingerprints averages 220 ms/query, making chemfp one of the fastest CPU-based similarity search implementations. Modern CPUs are fast enough that memory bandwidth and latency are now important factors. Single-threaded search uses most of the available memory bandwidth. Sorting the fingerprints by popcount improves memory coherency, which when combined with 4 OpenMP threads makes it possible to construct an N × N similarity matrix for 1 million fingerprints in about 30 min. These observations may affect the interpretation of previous publications which assumed that search was strongly CPU bound. The chemfp project funding came from selling a purely open-source software product. Several product business models were tried, but none proved sustainable. Some of the experiences are discussed, in order to contribute to the ongoing conversation on the role of open source software in cheminformatics.

Design and Implementation of Hybrid FIR Filters using Vedic Multiplier and Fast Adders

FIR (Finite Impulse Response) filters play a significant role in the field of Digital Signal Processing (DSP) to eliminate noise suppression in Electro Cardio Graph (ECG), Imaging devices and the signal stored in analog media. So filter evaluation is accomplished to reduce the noise level. The Filter passes only the desired frequency to pass thereby reducing distortion in the processed signal during measurement. The FIR filter comprises of basic units like adders, multipliers and the delay element for its operations.FIR and IIR are the two types of digital filters chosen based on the range of inputs, complexity and size requirement. Multipliers and adders play a vital role in deterring the performance of FIR filter. In this work, we design and analyze different multiplier and adder for high-performance Fir filter implementation. The Vedic Mathematics is the methods containing 16 Sutras to aid fast mental calculations. In this work, we propose modified Anurupye Vedic multiplier methods with Kogge Stone fast adder for implementation in the direct form FIR filter. This approach provides 1.5% decrease in delay and 10.2% reduced in power, hence increasing speed marginally than previous methods. Along with low power consumption in Very High-Speed Hardware Description Language (VHDL), all the adders and the multiplier topologies are Synthesized using (Xilinx Spartan – 6 FPGA) Trainer Kit and the proposed 8 – Tap FIR filter is executed using this Board.

Quantitative analysis of spectroscopic low energy electron microscopy data: High-dynamic range imaging, drift correction and cluster analysis

For many complex materials systems, low-energy electron microscopy (LEEM) offers detailed insights into morphology and crystallography by naturally combining real-space and reciprocal-space information. Its unique strength, however, is that all measurements can easily be performed energy-dependently. Consequently, one should treat LEEM measurements as multi-dimensional, spectroscopic datasets rather than as images to fully harvest this potential. Here we describe a measurement and data analysis approach to obtain such quantitative spectroscopic LEEM datasets with high lateral resolution. The employed detector correction and adjustment techniques enable measurement of true reflectivity values over four orders of magnitudes of intensity. Moreover, we show a drift correction algorithm, tailored for LEEM datasets with inverting contrast, that yields sub-pixel accuracy without special computational demands. Finally, we apply dimension reduction techniques to summarize the key spectroscopic features of datasets with hundreds of images into two single images that can easily be presented and interpreted intuitively. We use cluster analysis to automatically identify different materials within the field of view and to calculate average spectra per material. We demonstrate these methods by analyzing bright-field and dark-field datasets of few-layer graphene grown on silicon carbide and provide a high-performance Python implementation.

Developing Efficient Implementations of Shortest Paths and Page Rank Algorithms for NEC SX-Aurora TSUBASA Architecture

The main goal of this paper is to demonstrate that the newest generation of NEC SX-Aurora TSUBASA architecture can perform large-scale graph processing extremely efficiently. This paper proposes approaches, which can be used for the development of high-performance vector-oriented implementations of page rank and shortest paths algorithms, including vectorised graph storage format, efficient vector-friendly graph traversals, optimised cache-aware memory accesses and efficient load-balancing. The developed implementations are optimised according to the most important features and properties of SX-Aurora architecture, which allows them achieve up to 15 times better performance compared to the optimised Intel Skylake parallel implementations and up to 5 times better performance compared to NVGRAPH library implementations for Pascal GPU architecture.

GenSeq+: A Scalable High-Performance Accelerator for Genome Sequencing.

Genome sequencing is one of the most challenging problems in computational biology and bioinformatics. As a traditional algorithm, the string match meets a challenge with the development of the massive volume of data because of gene sequencing. Surveys show that there will be a huge amount of short read segments during the process of gene sequencing and the need for a highly efficient is urgent. As a classic fast and exact single pattern matching algorithm, Knuth-Morris-Pratt (KMP) algorithm has been demonstrated in network security and computational biology. However, with the increasing amount of data in the modern society, it becomes increasingly important and essential to provide a High-performance implementation of KMP algorithm. In this article, we implement a scalable KMP accelerator based on FPGA, named GeneKMP. The accelerator is composed of different computing units to achieve a pipelined organization for higher throughput with satisfying scalability. A novel programming model is provided to alleviate the burden of the high-level programmers. We provide a greedy-based partitioning algorithm for the software/hardware design paradigms. Experimental results on the state-of-the-art Xilinx FPGA hardware prototype show that our accelerator can achieve up to a promising speedup with insignificant hardware cost and power consumption.

Strategy Implementation Practices and Performance of Selected Evangelical Churches in Nairobi City County, Kenya

Every entity seeks accomplish its set goals, mandate and the reason for which it is established. The concept of organizational performance refers to the degree of achievement of the organization’s objectives, which is critical to its success and sustainability. The manner in which an organization implements its strategic plan largely determines the resultant success in the achievement of its strategic objectives. The primary objective of this study was to determine the influence of strategy implementation practices on the performance of select evangelical churches within Nairobi County. The specific objectives of the study were to investigate how organizational structure influences performance; examine the influence of resource allocation on overall performance; to establish the extent to which top management commitment affects performance and; to assess the influence of organizational culture on the performance of select evangelical churches in Nairobi City County. The variables of strategy implementation studied were organizational structure, resource allocation, top management commitment and organizational culture. The study was anchored on Burke and Litwin causal model and the Seven-S Model. The study adopted a descriptive research design and focused on a variety of respondents drawn from select evangelical churches within Nairobi City County - Christ is the Answer Ministries, Nairobi Baptist Church, Nairobi Chapel, and Parklands Baptist Church. The study targeted a population of 400 comprising of pastors, employees, church leaders, volunteers and members. A sample of 20% was applied generating a sample size of 80. Relevant data was gathered using structured questionnaires with both open and closed-ended questions. Qualitative data analysis involved explanation of information obtained from the empirical literature and required the use of numeric measures to the scores of the various responses. This was done with the aid of SPSS. The output of the analysis was presented in tables and charts, and interpretations made based on the research objectives. Generalizations of the results were made. The study established that organizational structure, resource allocation, top management commitment and organizational culture have a significant influence on the performance of evangelical churches. The study recommended that churches should develop organizational structures supportive of strategy implementation. It further recommended that the resources available should be focused on priority activities for optimum performance. In addition, the management should have a supportive and committed attitude towards strategy implementation to promote organizational success. It further recommended that churches create and uphold a positive institutional culture that supports high performance and effective implementation of the strategy.

A Survey on FPGA Support for the Feasible Execution of Virtualized Network Functions

Network Functions Virtualization (NFV) has received considerable attention in the past few years, both from industry and academia, due to its potential for reducing capital and operational expenditures, thus enabling faster innovation in networks. NFV proposes decoupling network functions from fixed hardware platforms and implementing them as virtual machines on off-the-shelf servers. Although potentially able to provide the mentioned benefits, software-based implementations of compute-intensive network functions still struggle to perform at the desired speed, especially when requiring line-rate processing for ever-faster communication links. To address this, hardware acceleration can be used to improve the throughput and latency of virtualized network functions (VNFs). In order to provide the advantages foreseen for NFV, however, such accelerators cannot be fixed and application-specific hardware, since they need to cope with new VNFs as well as fluctuations in demand. In this context, Field-Programmable Gate Arrays (FPGAs) are particularly suitable, since they are able to provide high-performance implementations of network functions and they are completely reprogrammable, thereby being able to implement different VNFs even after deployment. There have been many recent efforts to enable the use of FPGAs in the NFV context, including efficient implementations of network functions on FPGAs, platforms to manage the integration and coexistence of multiple VNFs on an FPGA, and high-level synthesis tools especially tailored to ease the programming of VNFs for FPGAs. In this work we survey previous work covering these aspects, and discuss the main open research challenges that must be addressed before FPGA adoption in NFV infrastructures becomes effectively seamless and efficient.

Coordinated DMA: Improving the DRAM Access Efficiency for Matrix Multiplication

High performance implementation of matrix multiplication is essential for scientific computing. The memory access procedure is quite possible to be the bottleneck of matrix multiplication. The widely used GotoBLAS GEMM implementation divides the integral matrix into several partitions to be assigned to different cores for parallelization. Traditionally, each core deploys a DMA transfer to access its own partition in the DRAM memory. However, deploying an independent DMA transfer for each core cannot efficiently exploit the inter-core locality. Also, multiple concurrent DMA transfers interfere with each other, further reducing the DRAM access efficiency. We observe that the same row of neighboring partitions is in the same DRAM page, which means that there is significant locality inherent in the address layout. We propose the coordinated DMA to efficiently exploit the locality. It invokes one transfer to serve all cores and moves data in a row-major manner to improve the DRAM access efficiency. Compared with a baseline design, the coordinated DMA improves the bandwidth by 84.8 percent and reduces DRAM energy consumption by 43.1 percent for micro-benchmarks. It achieves higher performance for the GEMM and Linpack benchmark. With much less hardware costs, the coordinated DMA significantly outperforms an out-of-order memory controller.

Optimizing Deep Learning RNN Topologies on Intel Architecture

Recurrent neural network (RNN) models have been found to be well suited for processing temporal data. In this work, we present an optimized implementation of vanilla RNN cell and its two popular variants: LSTM and GRU for Intel Xeon architecture. Typical implementations of these RNN cells employ one or two large matrix multiplication (GEMM) calls and then apply the element-wise operations (sigmoid/tanh) onto the GEMM results. While this approach is easy to implement by exploiting vendor-optimized GEMM library calls, the data reuse relies on how GEMMs are parallelized and is sub-optimal for GEMM sizes stemming from small minibatch. Also, the element-wise operations are exposed as a bandwidth-bound kernel after the GEMM which is typically a compute-bound kernel. To address this discrepancy, we implemented a parallel blocked matrix GEMM in order to (a) achieve load balance, (b) maximize weight matrix reuse, (c) fuse the element-wise operations after partial GEMM blocks are computed and while they are hot in cache. Additionally, we bring the time step loop in our cell to further increase the weight reuse and amortize the overhead to transform the weights into blocked layout. The results show that our implementation is generally faster than Intel MKL-DNN library implementations, e.g. for RNN, forward pass is up to ~3× faster whereas the backward/weight update pass is up to ~5× faster. Furthermore, we investigate high-performance implementations of sigmoid and tanh activation functions that achieve various levels of accuracy. These implementations rely on minimax polynomial approximations, rational polynomials, Taylor expansions and exponential approximation techniques. Our vectorized implementations can be flexibly integrated into deep learning computations with different accuracy requirements without compromising performance; in fact, these are able to outperform vectorized and reduced accuracy vendor-optimized (Intel SVML) libraries by 1.6–2.6× while speep up over GNU libm is close to two orders of magnitude. All our experiments are conducted on Intel’s latest CascadeLake architecture.

Optimizing Bit-Serial Matrix Multiplication for Reconfigurable Computing

Matrix-matrix multiplication is a key computational kernel for numerous applications in science and engineering, with ample parallelism and data locality that lends itself well to high-performance implementations. Many matrix multiplication-dependent applications can use reduced-precision integer or fixed-point representations to increase their performance and energy efficiency while still offering adequate quality of results. However, precision requirements may vary between different application phases or depend on input data, rendering constant-precision solutions ineffective. BISMO, a vectorized bit-serial matrix multiplication overlay for reconfigurable computing, previously utilized the excellent binary-operation performance of FPGAs to offer a matrix multiplication performance that scales with required precision and parallelism. We show how BISMO can be scaled up on Xilinx FPGAs using an arithmetic architecture that better utilizes six-input LUTs. The improved BISMO achieves a peak performance of 15.4 binary TOPS on the Ultra96 board with a Xilinx UltraScale+ MPSoC.

SWIRL: High-performance many-core CPU code generation for deep neural networks

Deep neural networks (DNNs) have demonstrated effectiveness in many domains including object recognition, speech recognition, natural language processing, and health care. Typically, the computations involved in DNN training and inferencing are time consuming and require efficient implementations. Existing frameworks such as TensorFlow, Theano, Torch, Cognitive Tool Kit (CNTK), and Caffe enable Graphics Processing Unit (GPUs) as the status quo devices for DNN execution, leaving Central Processing Unit (CPUs) behind. Moreover, existing frameworks forgo or limit cross layer optimization opportunities that have the potential to improve performance by significantly reducing data movement through the memory hierarchy. In this article, we describe an alternative approach called SWIRL, a compiler that provides high-performance CPU implementations for DNNs. SWIRL is built on top of the existing domain-specific language (DSL) for DNNs called LATTE. SWIRL separates DNN specification and its schedule using predefined transformation recipes for tensors and layers commonly found in DNN layers. These recipes synergize with DSL constructs to generate high-quality fused, vectorized, and parallelized code for CPUs. On an Intel Xeon Platinum 8180M CPU, SWIRL achieves performance comparable with Tensorflow integrated with MKL-DNN; on average 1.00× of Tensorflow inference and 0.99× of Tensorflow training. It also outperforms the original LATTE compiler on average by 1.22× and 1.30× on inference and training, respectively.

STEEL-RT: combining single task–single executor model and expanded scheduling to ease heterogeneity exploitation

The ever-increasing complexity in terms of heterogeneity and available parallelism of modern architectures, together with the growing software ecosystem in terms of application libraries and runtime systems are posing a new challenge in terms of programmability on top of the already difficult task of extracting high parallel performance. With the goal of simplifying the programmability at the extreme, we first present the single task–single executor (STSE) model, in which the execution entry point consists solely on a single task assigned to an abstract execution context or executor, representing the whole system platform. As a second contribution, we introduce the expanded scheduling operations that endow executors with additional runtime task scheduling capabilities, and explain how executors can be composed to express and exploit different architectural features at run time under the framework of a single/multiple–task/executor taxonomy. As a result, we introduce STEEL, a novel programming model built on these concepts and STEEL-RT, a coupled high-performance runtime implementation for it. We illustrate the potential of STEEL by means of runtime experiments on a modern heterogeneous architecture, showing that complex and efficient heterogeneous executions are accessible from a STSE approach.

High-performance Implementation of Elliptic Curve Cryptography Using Vector Instructions

Elliptic curve cryptosystems are considered an efficient alternative to conventional systems such as DSA and RSA. Recently, Montgomery and Edwards elliptic curves have been used to implement cryptosystems. In particular, the elliptic curves Curve25519 and Curve448 were used for instantiating Diffie-Hellman protocols named X25519 and X448. Mapping these curves to twisted Edwards curves allowed deriving two new signature instances, called Ed25519 and Ed448, of the Edwards Digital Signature Algorithm. In this work, we focus on the secure and efficient software implementation of these algorithms using SIMD parallel processing. We present software techniques that target the Intel AVX2 vector instruction set for accelerating prime field arithmetic and elliptic curve operations. Our contributions result in a high-performance software library for AVX2-ready processors. For example, our library computes digital signatures 19% (for Ed25519) and 29% (for Ed448) faster than previous optimized implementations. Also, our library improves by 10% and 20% the execution time of X25519 and X448, respectively.

Design and Implementation of High Performance and Low Power Mixed Logic Line Decoders

The decoders are widely used in the logical circuits, data transfer circuits and analog to digital conversions. A mixed logic design methods for the line decoders are used to combining the transmission gate logic, pass transistor logic, and complementary metal-oxide semiconductor (CMOS) technology provides desired operation and performance. A novel topology is presented for the 2 to 4 decoder requires a fourteen transistor topology aiming on reducing the transistor count and operating power and a fifteen transistor topology aiming on high power and low delay performance. The standard and inverting decoders are designed in each of the case, gives a total of four new designs circuits. All the proposed decoders have compact transistor count compared to their conservative CMOS technologies. Finally, a variety of proposed designs present a noteworthy improvement in operating power and propagation delay, outperforming CMOS in almost all the cases.