High-performance Electronic Systems Research Articles

Low Power Sub Threshold QDI Kogge Stone Adder using Sense Amplifier Lector based Half Buffer Cell Templates

Nowadays power consumption has the highest priority in designing high-performance electronics systems. The main purpose of this paper is to present a 16-bitKogge-Stone Adder where the low control operation is attained by the decrease of exchanging action. In this paper, we propose a method called Sense amplifier Lector based Half-Buffer (SALHB) by exemplifying Sense Amplifier Half Buffer (SAHB) with LECTOR algorithm to lessen leakage current in circuit structure. A 16-piece Kogge Stone Adder (KSA) is structured and actualized utilizing an asynchronous Quasi-Delay-Insensitive cell configuration approach known as the SALHB algorithm. Generally, SAHB is an asynchronous QDI configuration approach which applies 4-phase signaling protocol and sub-edge operation to obtain low control dissipation and rapid of operation. Additionally, LECTOR algorithm is applied to SAHB configuration approach through which leakage current can be decreased further to a great degree. A portion of the asynchronous QDI cell templates are Pre-charged Half-buffer(PCHB) and Autonomous signal validity Half-buffer(ASVHB), as both the templates, use completion detector circuits which lead to high power dissipation and large area overhead. SAHB design surpasses these drawbacks. But, SAHB has more leakage current. Hence, SALHB method was proposed to overcome the problem of high leakage current. In this paper, the performance of KSA is analyzed in terms of power, delay, energy, rise time, fall time, settle time, duty cyle, throughput and slew rate.

Material-Selective Doping of 2D TMDC through AlxOy Encapsulation.

For the integration of two-dimensional (2D) transition metal dichalcogenides (TMDC) with high-performance electronic systems, one of the greatest challenges is the realization of doping and comprehension of its mechanisms. Low-temperature atomic layer deposition of aluminum oxide is found to n-dope MoS2 and ReS2 but not WS2. Based on electrical, optical, and chemical analyses, we propose and validate a hypothesis to explain the doping mechanism. Doping is ascribed to donor states in the band gap of AlxOy, which donate electrons or not, based on the alignment of the electronic bands of the 2D TMDC. Through systematic experimental characterization, incorporation of impurities (e.g., carbon) is identified as the likely cause of such states. By modulating the carbon concentration in the capping oxide, doping can be controlled. Through systematic and comprehensive experimental analysis, this study correlates, for the first time, 2D TMDC doping to the carbon incorporation on dielectric encapsulation layers. We highlight the possibility to engineer dopant layers to control the material selectivity and doping concentration in 2D TMDC.

Practical Implementation of Memristor-Based Threshold Logic Gates

Current advances in emerging memory technologies enable novel and unconventional computing architectures for high-performance and low-power electronic systems, capable of carrying out massively parallel operations at the edge. One emerging technology, ReRAM, also known to belong in the family of memristors (memory resistors), is gathering attention due to its attractive features for logic and in-memory computing and benefits which follow from its technological attributes, such as nanoscale dimensions, low-power operation, and multi-state programming. At the same time, the design with CMOS is quickly reaching its physical and functional limitations, and further research toward novel logic families, such as threshold logic gates (TLGs), is scoped. In this paper, we introduce a physical implementation of a memristor-based current-mode TLG (MCMTLG) circuit and validate its design and operation through multiple experimental setups. We demonstrate two-input, three-input, and four-input MCMTLG configurations and showcase their reconfiguration capability. This is achieved by varying memristive weights arbitrarily for shaping the classification decision boundary, thus showing a promise as an alternative hardware-friendly implementation of artificial neural networks. Through the employment of real memristor devices as the equivalent of synaptic weights in TLGs, we are realizing components that can be used toward an in silico classifier.

Numerical Study of Performance of Porous Fin Heat Sink of Functionally Graded Material for Improved Thermal Management of Consumer Electronics

The ever-increasing demand for high-performance electronic and computer systems has unequivocally called for increased microprocessor performance. However, increasing microprocessor performance requires increasing the power and on-chip power density of the microprocessor, both of which are associated with increased heat dissipation. In recent times, thermal management of electronic systems has gained intense research attention due to increased miniaturization trend in the electronics industry. In this paper, we present a numerical study on the performance of a convective–radiative porous heat sink with functionally graded material (FGM) for improved cooling of various consumer electronics. For the theoretical investigation, the thermal property of the FGM is assumed as a linear and power-law function. We solved the developed thermal models using the Chebyshev spectral collocation method (CSCM). The effects of inhomogeneity index of FGM and convective and radiative parameters on the thermal behavior of the porous heat sink are investigated. This paper shows that increase in the inhomogeneity index of FGM and convective and radiative parameters improves the thermal efficiency of the porous fin heat sink. Moreover, for all values of Nc and Rd, the temperature gradient along the fin of FGM is negligible compared to HM fin in both linear and power-law functions. For comparison, the thermal predictions made in this paper using CSCM agree excellently with the established results of Runge–Kutta with shooting and homotopy analytical method.

Ultrahigh Evaporative Heat Fluxes in Nanoconfined Geometries.

Advancement in high-performance photonics/electronics devices has boosted generated thermal energy, making thermal management a bottleneck for accelerated innovation in these disciplines. Although various methods have been used to tackle the thermal management problem, evaporation with nanometer fluid thickness is one of the most promising approaches for future technological demands. Here, we studied thin-film evaporation in nanochannels under absolute negative pressure in both transient and steady-state conditions. We demonstrated that thin-film evaporation in nanochannels can be a bubble-free process even at temperatures higher than boiling temperature, providing high reliability in thermal management systems. To achieve this bubble-free characteristic, the dimension of nanochannels should be smaller than the critical nucleolus dimension. In transient evaporative conditions, there is a plateau in the velocity of liquid in the nanochannels, which limits the evaporative heat flux. This limit is imposed by liquid viscous dissipation in the moving evaporative meniscus. In contrast, in steady-state condition, unprecedented average interfacial heat flux of 11 ± 2 kW cm-2 is achieved in the nanochannels, which corresponds to liquid velocity of 0.204 m s-1. This ultrahigh heat flux is demonstrated for a long period of time. The vapor outward transport from the interface is both advective and diffusion controlled. The momentum transport of liquid to the interface is the limiting physics of evaporation at steady state. The developed concept and platform provide a rational route to design thermal management technologies for high-performance electronic systems.

Ultra-High Density, Thin-Film Tantalum Capacitors with Improved Frequency Characteristics for MHz Switching Power Converters

High-density passive components are needed for continued miniaturization of complex high-performance electronic systems. Tantalum (Ta) capacitors provide some of the highest volumetric densities achieved due to their combination of high-surface area and relatively high dielectric constant, but suffer from low frequency stability and large form-factors due to the electrode design. In this paper, a printed thin-film tantalum capacitor design is presented. Tantalum capacitor arrays of 1 μF/mm2 up to and beyond 1 MHz. The improved frequency stability comes from the ultra-thin structure of the capacitors, which reduces the path length of the charging and discharging current. The capacitors showed low equivalent series resistance and consistent electrical performance before and after thermal moisture testing at 65°C and 95% relative humidity for 500 h and 1000 h. Due to the ultra-low form-factor, the thin-film Ta capacitor technology can be extended to highly-miniaturized power converters with efficient substrate- or wafer-scale integration.

Adding a stretchable deep-trap interlayer for high-performance stretchable triboelectric nanogenerators

The main approach to enhancing the electrical output performance of triboelectric nanogenerators (TENGs) has been focused to increase of triboelectric charge generation. However, there have been few studies on achieving effective electrostatic induction and conserving the triboelectric charges. This study reports that an interlayer containing deep charge traps of large trap density can conserve the surface charges for long period of time and increase the surface potential that can be obtained. This study suggests polydimethylsiloxane (PDMS) added between a charge generation layer and an electrode as an effective material candidate for the interlayer. The PDMS interlayer greatly enhanced the output power density of TENGs (20.8 W/m2 by gentle tapping), which is 173-fold increase compared to TENGs without the interlayer. Surprisingly, the PDMS interlayer resulted in triboelectric performance even between identical surfaces, which is owing to the enhanced charge conservation by the interlayer. This study demonstrates a high-performance stretchable single-electrode TENG (S-TENG) which shows stable high performance at 50% uniaxial strain during repeated stretch cycles. The results in this study provide insight to material design for achieving high-performance stretchable self-powered electronic systems.

Flexible Multimode Polymer Waveguide Arrays for Versatile High-Speed Short-Reach Communication Links

Optical interconnects play an important role in enabling high-speed short-reach communication links within next-generation high-performance electronic systems. Multimode polymer waveguides in particular allow the formation of high-capacity optical backplanes and cost-effective board-level optical interconnects. Their formation on flexible substrates offers significant practical advantages and enables their deployment in environments where shape and weight conformity become particularly important, such as in cars and aircraft. However, bending and twisting of flexible multimode waveguides can have a significant effect on their optical transmission performance due to mode loss and mode coupling. Moreover, the magnitude of the induced effects strongly depends on the launch conditions employed. In this paper, therefore, we present detailed loss, crosstalk, and bandwidth studies on flexible multimode waveguide arrays for different launch conditions regarding their use in real-world systems. The minimum radius to achieve a 1 dB excess bending loss is obtained for each launch condition as well as the crosstalk degradation due to bending. It is shown that for a 50 μm MMF input, a 6 mm bending radius is required for excess losses below 1 dB, while crosstalk below −35 dB is obtained in adjacent waveguides even under strong bending. Moreover, it is found that twisting has a small effect on the loss and crosstalk performance of the samples. Excess twisting loss less than 0.1 dB and crosstalk of −40 dB are obtained for three full 360° turns under a 50 μm MMF launch. Finally, the bandwidth studies carried out on the samples indicate than no significant bandwidth degradation is induced due to sample bending, with bandwidth-length product values larger than 150 GHz × m obtained for restricted launches. The set of results presented herein specify the deployment of this flexible polymer multimode waveguide technology in real-world systems and demonstrate its strong potential to implement low-loss high-bandwidth optical interconnects.

Vacuum-assisted bilayer PEDOT:PSS/cellulose nanofiber composite film for self-standing, flexible, conductive electrodes

Sustainable cellulose nanofiber (CNF)-based composites as functional conductive materials have garnered considerable attention recently for their use in soft electronic devices. In this work, self-standing, highly flexible, and conductive PEDOT:PSS-CNF composite films were developed using a simple vacuum-assisted filtration method. Two different composite films were successfully fabricated and then tested: 1) a single-layer composite composed of a mixture of PEDOT:PSS and CNF phases and 2) a bilayer composite composed of an upper PEDOT:PSS membrane layer and a CNF matrix sub-layer. The latter composite was constructed by electrostatic/hydrogen bonding interactions between PEDOT:PSS and CNFs coupled with sequential vacuum-assisted filtration. Our results demonstrated that the resultant bilayer composite film exhibited a competitive electrical conductivity (ca. 22.6Scm−1) compared to those of previously reported cellulose-based composites. Furthermore, decreases in the electrical properties were not observed in the composite films when they were bent up to 100 times at an angle of 180° and bent multiple times at an angle of 90°, clearly demonstrating their excellent mechanical flexibility. This study provides a straightforward method of fabricating highly flexible, lightweight, and conductive films, which have the potential to be used in high-performance soft electronic systems.

Freeform Compliant CMOS Electronic Systems for Internet of Everything Applications

The state-of-the-art electronics technology has been an integral part of modern advances. The prevalent rise of the mobile device and computational technology in the age of information technology offers exciting applications that are attributed to sophisticated, enormously reliable, and most mature CMOS-based electronics. We are accustomed to high performance, cost-effective, multifunctional, and energy-efficient scaled electronics. However, they are rigid, bulky, and brittle. The convolution of flexibility and stretchability in electronics for emerging Internet of Everything application can unleash smart application horizon in unexplored areas, such as robotics, healthcare, smart cities, transport, and entertainment systems. While flexible and stretchable device themes are being remarkably chased, the realization of the fully compliant electronic system is unaddressed. Integration of data processing, storage, communication, and energy management devices complements a compliant system. Here, a comprehensive review is presented on necessity and design criteria for freeform (physically flexible and stretchable) compliant high-performance CMOS electronic systems.

A high performance CNFET-based operational transconductance amplifier and its applications

High performance electronic systems face several challenges in driving innovative integrated circuits when the internal transistors are scaled down below 45 nm. Carbon nanotube field effect transistors (CNFETs) are considered as excellent candidates for building energy-efficient electronic systems in the near future, due to their unique characteristics such as ballistic transport, scalability, and better channel electrostatics. In this paper, a new high performance operational transconductance amplifier (OTA) based on 32 nm CNFET devices is presented. The proposed OTA maintains a highly linear wide continuous tuning range and a wide frequency response range, enabled by splitting the linear voltage-to-current conversion and tuning two different blocks. As an application, a universal second-order transconductance-capacitor (Gm ź C) filter realized using the OTA is introduced. Simulation results show that the CNFET-based OTA offers very a low current consumption of 2.35 μA from a ± 0.9 V power supply, achieves a bandwidth of 9.5 MHz, and has an input dynamic range of ± 0.2 V.

Effect of Gold on the Microstructural Evolution and Integrity of a Sintered Silver Joint

There is a need for next-generation, high-performance power electronic packages and systems employing wide-bandgap devices to operate at high temperatures in automotive and electric grid applications. Sintered silver joints are currently being evaluated as an alternative to Pb-free solder joints. Of particular interest is the development of joints based on silver paste consisting of nano- or micron-scale particles that can be processed without application of external pressure. The microstructural evolution at the interface of a pressureless-sintered silver joint formed between a SiC die with Ti/Ni/Au metallization and an active metal brazed (AMB) substrate with Ag metallization at 250°C has been evaluated using scanning electron microscopy (SEM), x-ray microanalysis, and x-ray photoelectron spectroscopy (XPS). Results from focused ion beam (FIB) cross-sections show that, during sintering, pores in the sintered region near to the Au layer tend to be narrow and elongated with long axis oriented parallel to the interface. Further densification results in formation of many small, relatively equiaxed pores aligned parallel to the interface, creating a path for easy crack propagation. X-ray microanalysis results confirm interdiffusion between Au and Ag and that a region with poor mechanical strength is formed at the edge of this region of interdiffusion.

Decal Electronics: Printable Packaged with 3D Printing High‐Performance Flexible CMOS Electronic Systems

High-performance complementary metal oxide semiconductor electronics are flexed, packaged using 3D printing as decal electronics, and then printed in roll-to-roll fashion for highly manufacturable printed flexible high-performance electronic systems. As a service to our authors and readers, this journal provides supporting information supplied by the authors. Such materials are peer reviewed and may be re-organized for online delivery, but are not copy-edited or typeset. Technical support issues arising from supporting information (other than missing files) should be addressed to the authors. Please note: The publisher is not responsible for the content or functionality of any supporting information supplied by the authors. Any queries (other than missing content) should be directed to the corresponding author for the article.

Guest Editorial: IEEE Transactions on Computers and IEEE Transactions on Nanotechnology Joint Special Section on Defect and Fault Tolerance in VLSI and Nanotechnology Systems

The papers in this special issue focus on defect and fault tolerance in VLSI and nanotechnology systems. With the increasing demand for ever smaller, portable, energy-efficient and high-performance electronic systems, scaling of CMOS technology continues. As CMOS scaling approaches physical limits, continued innovation in materials, manufacturing processes, device structures and design paradigms have been necessary. High-k oxide and metal-gate stack were introduced to address oxide leakage; thin body undoped channels, and multiple-gate structures were introduced to mitigate subthreshold leakage; restricted design rules were introduced to improve layout efficiency; yet CMOS technology continues to be challenged in the areas of device aging and reliability. While CMOS is expected to be the dominant semiconductor technology for the foreseeable future, for reasons that are both technological and financial, alternatives to CMOS technology are attracting attention from the researchers.

Guest Editorial IEEE Transactions on Computers and IEEE Transactions on Nanotechnology Joint Special Section on Defect and Fault Tolerance in VLSI and Nanotechnology Systems

The papers in this special section focus on the technology and applications supported by defect/fault tolerance in very large scale integration and nanotechnology systems. With increasing demand for ever smaller, portable, energy-efficient, and high-performance electronic systems, scaling of CMOS technology continues. As CMOS scaling approaches physical limits, continued innovation in materials, manufacturing processes, device structures, and design paradigms have been necessary. High-κ oxide and metal-gate stack were introduced to address oxide leakage; thin body undoped channels, and multiple-gate structures were introduced to mitigate subthreshold leakage; restricted design rules were introduced to improve layout efficiency; yet CMOS technology continues to be challenged in the areas of device aging and reliability. While CMOS is expected to be the dominant semiconductor technology for the foreseeable future—due to for reasons that are both technological and financial, alternatives to CMOS technology are attracting attention from the researchers.

Proposing and verifying a security protocol for hash function-based IoT communication system

Internet of things (IoT) has recently drawn much attention around the world. Technological development in relevant industries has facilitated great strides in the advancement of multifunctional high-performance electronic communication system. IoT technology conceptually encompasses information service, transmission, identification, hardware, infrastructure, embedded, security, material and network technologies. In particular, the importance of security technology is highlighted in IoT technology due in part to the concerns over hacking attacks leading to system malfunction, remote control and authorization in the guise of administrators. Thus, mutual authentication and security are regarded as the overarching aspect of communication. In the same vein, secure communication protocols have extensively been explored in the field of security. The present paper designed a secure communication protocol using hash locks, timestamps, agent passwords and security keys. Unlike most of previous studies intended to prove the security of protocols using mathematical theorems, the present paper established the security of the proposed protocol against a range of intruders' attacks by testing it using a formal verification tool, Casper/FDR. The test results confirmed the security of the proposed protocol in terms of safety, deadlock and livelock.

Guest Editorial: Special Section on Circuit and System Design Methodologies for Emerging Technologies

The demand for ever smaller, portable, energy-efficient and high-performance electronic systems has been the primary driver for CMOS technology scaling. As CMOS scaling approaches physical limits, it has been fraught with challenges that required introduction of newer materials, manufacturing processes and device structures. High- $\kappa$ oxide and metal-gate stack was introduced to mitigate oxide leakage which became a significant concern for sub-65nm CMOS technologies. Thin body, undoped channels, and multiple-gate structures were introduced to mitigate subthreshold leakage as battery life for mobile devices rose to prominence. 3D transistors such as double-gate FinFET and trigate transistors have been introduced to improve ON current and reduce subthreshold leakage without compromising layout efficiency that is crucial for device density which leads to lower costs. These innovations have allowed sustained scaling of CMOS technology which will continue to dominate semiconductor manufacturing for reasons that are both technological and financial. In CMOS technology, charge conveys logic information. Movement of charge is central to computation and storage, which entails a minimum energy dissipation of the order kB $\ast$ T per switching event. It has been argued that energy dissipation defines the fundamental limit of CMOS scaling.

Experimental Investigation of a Direct Liquid Immersion Cooled Prototype for High Performance Electronic Systems

As the demand grows for electronics to become faster and more compact, the expectation for tomorrow’s data center is no different. Like many of the current high performance data center installations, design considerations on all scales must be taken into account. The proposed solution does just this by looking at the entire cooling approach from the chip level all the way to the plenum level. The solution’s enclosure, where all the heated elements are immersed in either FC-72 or Novec 649, has dimensions of $150~{\rm mm} \times 300~{\rm mm} \times 38$ mm ( $H \times L \times W$ ). The design is versatile allowing for either flow or pool boiling heat transfer. Under pool boiling conditions, heat transfer coefficients as high as 11.5 kW/ $\text{m}^{2}\,\cdot \,\text{K}$ were achieved with surface enhancements and maximum power dissipations as high as 320 W were yielded as chip temperatures were roughly 58 °C, well below typical operating conditions. With the introduction of dielectric fluid flow within the enclosure, maximum power dissipations achieved increased substantially, reaching 605 W, which corresponds to a volumetric power dissipation of 0.354 W/cm3.

A RBF model for predicting the pool boiling behavior of nanofluids over a horizontal rod heater

Pool boiling is an effective means of heat transfer which can handle high fluxes in boiling while maintaining minimum temperature differences over the heated surface. Addition of nanoparticles and surfactants to the base fluid are potential methods for enhancing the pool boiling heat transfer coefficient which can be useful in thermal management of complex and high performance electronic systems. This communication provides a Radial Basis Function (RBF) model to predict the behavior of a surfactant and three different types of nanoparticles on pool boiling heat transfer of water over a horizontal rod heater. In this model, the inputs include experimental condition parameters of heat flux, type of water (distilled or treated water), and concentration of SDS (Sodium Dodecyl Sulfate), nano-alumina, nano-silica with two different particle sizes, and nano-Zinc Oxide. Genetic algorithm is used for determination of the optimum values. Statistical error analysis with different parameters is also implemented for validation of the predictive model. The model is based on three sets of experiments. The effects of two different types of water, SDS and/or nano-alumina (a), the effects of two particle sizes of nano-silica (b), and the effect of combination of nano-Zinc oxide and SDS (c) on pool boiling heat transfer of water as based fluid. In all above sets of tests, the effects of the nanoparticles and SDS coated on the surface of the heater were investigated by repeating the experiments after cleaning all parts of the device except its heater surface. Furthermore, Surface Tension and Dynamic Viscosity, the two crucial thermo-physical characteristics of fluids, were determined for justifying the behavior of the materials used in the experiments. The results showed that the treated water has a better boiling performance in comparison to distilled water; the presence of SDS, Alumina, and the combination of Zinc oxide and SDS enhance the boiling performance of the base fluid; both kinds of nano-silica deteriorates the pool boiling heat coefficient of water and the smaller one has more reduction effect; the combination of the Zinc Oxide and SDS is the best coolant among the aforementioned ones. Finally, the experimental results are modeled using radial basis function neural networks and the outputs of the model are in great agreement with the experimental data.

Designing and verifying a P2P service security protocol in M2M environment

Multifunctional high-performance electronic systems in M2M(Machine-to-Machine) industry have been evolving substantially in tandem with the advancement of IT. M2M, standing for machine-to-machine communication, replaces people in cases where human intervention is hardly viable or in such fields as weather, environment or disasters where long-term monitoring is required. Yet, due to the nature of M2M devices involving wireless communication, they are exposed to intruders’ attacks. Thus, the overriding concern in M2M communication is mutual authentication and security. In this context, security communication protocols are considered worth exploring. This paper concerns designing a safe communication protocol by applying hash locks, random numbers and session keys. Instead of arguing for the security of the protocol based on mathematical theorem proving as most previous studies did, the present paper demonstrates the proposed protocol is safe against a variety of intruders’ attacks by formally verifying it using Casper/FDR. In short, the proposed protocol is verified in terms of safety, deadlock and livelock.