High Performance CMOS Devices Research Articles

Novel Approach to Reduce Source/Drain Series and Contact Resistance in High-Performance UTSOI CMOS Devices Using Selective Electrodeless CoWP or CoB Process

This letter reports a selective metal deposition process using an electrodeless technique for MOSFETs fabricated in an ultrathin silicon-on-insulator (UTSOI) substrate. A layer of metal (CoWP or CoB) is formed on the source and drain nickel and cobalt silicides without depositing on the dielectric spacers. Leakage current information, which is an indication of selectivity of the process, is presented in this letter. The shortest channel length of the UTSOI NMOSFETs is 20 nm, and the SOI thickness is 10 nm. The data show that excellent selectivity is achieved without increasing the leakage current of the transistors.

Influence of Temperature on Boron Concentration in SiGe-B Epitaxy

SiGe-B source/drain (S/D) epitaxy is successfully used in mass production of high performance CMOS device (1-2). Due to the difference in free energy across the SiGe-B/substrate interface, there is boron segregation at the interface (3-4). In addition, low level of contamination also contributes to the pile-up of boron at the interface (5). In PMOS device manufacturing, the excessive boron will diffuse into the channel region in the high temperature processes after EPI S/D, which adversely affects device performance (5). In this paper, influence of temperature on boron concentration in the bulk and at the interface is reported.

Thermal effects on 1H and 2H distributions determined by SIMS in atomic layer deposition of HfO 2 and Al 2O 3 using heavy water

Incorporation of deuterium using D 2O as the oxidant during the atomic layer deposition of high-k gate dielectric on silicon should lead, after post metal annealing, to a better passivation of defects and interface states than this obtained with hydrogen species. However, an optimised high-k/D 2O anneal is required for manufacturing high performance CMOS devices. This paper reports new investigations by SIMS on the deuterium incorporation inside thin HfO 2 and Al 2O 3 layers deposited by atomic layer deposition using HfCl 4 and trimethylaluminium (TMA), respectively and heavy water. A wide range of thermal treatments are investigated. The results highlight the hydrogen/deuterium isotope effect at different annealing temperatures. The deuterium profile shows a concentration peak at the high-k/substrate interface; however, the D dose is low and the interface peak becomes sharper at high temperature. This preferential incorporation of deuterium at high temperature could improve the interface quality and enhance the high-k device stability and reliability.

Front-End Process Technology for hp65/45 CMOS Devices

In order to obtain high performance CMOS devices, introduction of new technologies into the front-end fabrication process are required and therefore so-called technology boosters such as strained channel, metal gate, high-k gate dielectrics, thin body SOI, and multi-gate transistor, are proposed so far. Among these technologies, gate stack technology is common key issue for scaled CMOS devices. In this proceeding, we will discuss on high-k gate dielectrics and metal gate technology, and recent achievements of these technologies are reviewed.

Current Conduction and Dielectric Behavior of High k-Y2O3 Films Integrated with Si Using Chemical Vapor Deposition as a Gate Dielectric for Metal-Oxide-Semiconductor Devices

Integration of Y2O3 high-k thin film over Si as gate dielectric in high performance CMOS and high-density MOS memory storage capacitor devices is described. Y2O3 film growth by low-pressure chemical vapor deposition induces interfacial reactions and complex SiO2 − x layer growth. It has a graded structure, in crystalline-SiO2 form at Y2O3 side and amorphous SiO2 − x form at Si side. MIS devices based on Y2O3/SiO2-SiO2 − x composite dielectric integrated with Si show high frequency C-V behavior indicative of inversion to accumulation changes in capacitance. Observed bi-directional hysterisis in C-V is detrimental to the functioning of storage capacitor in memory function. Detailed investigation of this effect led to understanding of gate bias controlled emission of carriers as responsible mechanism. Observed anomalous increase in inversion capacitance at low frequency is attributed to additional charges transferred from SiO2 − x/Si interface states. Leakage current and injected charge carrier transport across bilayer interface is dominated by Poole-Frankel (PF) process at low fields and by Fowler-Nordhiem (FN) at high fields. This investigation provides a greater understanding of the complex nature of integration of Y2O3 films.

(Selective) Epitaxial Growth of Strained Si to Fabricate Low Cost and High Performance CMOS Devices

ABSTRACTTensile strained Si on SiGe Strain Relaxed Buffers (SRB) is an interesting candidate to increase both electron and hole mobility which results in improved device performance. Most of this work was/is based on thick (several μm), step-graded SRBs with or without Chemical Mechanical Polishing (CMP) planarisation. This approach bears several disadvantages such as issues with STI formation in the thick SiGe structure, and considerable self-heating effects due to the lower thermal conductivity of the SiGe material. Further, pMOS improvement requires SRBs with high Ge contents (> 30 %), which complicates device fabrication even more. To overcome these issues, we developed a new and cost efficient type of thin SRB (∼200 nm). The concept is based on the introduction of a thin carbon-containing layer during growth of a constant composition SiGe layer. The process relies on standard Chemical Vapor Deposition epitaxial technology without need for CMP. It is designed to allow both non-selective growth on blanket wafers and selective growth in the active area of structured wafers with Shallow Trench Isolation (STI). The selective epitaxial process for strained Si on thin SRBs proposed here, allows relatively simple and cost-effective fabrication of strained Si layers on existing STI structures without any process modification. Further, it offers a very flexible fabrication scheme to independently improve nMOS and pMOS devices. The SRB quality is comparable to the best reported in literature so far, with 70 % and 53 % mobility enhancements for long channel nMOSFETs on 22 % Ge SRBs grown on blanket and STI patterned wafers, respectively.

Characterization of 1.9- and 1.4-nm Ultrathin Gate Oxynitride by Oxidation of Nitrogen-implanted Silicon Substrate

For gate oxide thinned down to 1.9 and 1.4 nm, conventional methods of incorporating nitrogen (N) in the gate oxide might become insufficient in stopping boron penetration and obtaining lower tunneling leakage. In this paper, oxynitride gate dielectric grown by oxidation of N-implanted silicon substrate has been studied. The characteristics of ultrathin gate oxynitride with equivalent oxide thickness (EOT) of 1.9 and 1.4 nm grown by this method were analyzed with MOS capacitors under the accumulation conditions and compared with pure gate oxide and gate oxide nitrided by N/sub 2/O annealing. EOT of 1.9- and 1.4-nm oxynitride gate dielectrics grown by this method have strong boron penetration resistance, and reduce gate tunneling leakage current remarkably. High-performance 36-nm gate length CMOS devices and CMOS 32 frequency dividers embedded with 57-stage/201-stage CMOS ring oscillator, respectively, have been fabricated successfully, where the EOT of gate oxynitride grown by this method is 1.4 nm. At power supply voltage V/sub DD/ of 1.5 V drive current Ion of 802 /spl mu/A//spl mu/m for NMOS and -487 /spl mu/A//spl mu/m for PMOS are achieved at off-state leakage I/sub off/ of 3.5 nA//spl mu/m for NMOS and -3.0 nA//spl mu/m for PMOS.

High-performance strained-SOI CMOS devices using thin film SiGe-on-insulator technology

We have developed high-performance strained-SOI CMOS devices on thin film relaxed SiGe-on-insulator (SGOI) substrates with high Ge content (25%) fabricated by the combination of separation-by-implanted-oxygen (SIMOX) and internal-thermal-oxidation (ITOX) techniques without using SiGe buffer structures. The maximum enhancement of electron and hole mobilities of strained-SOI devices against the universal mobility amounts to 85 and 53%, respectively. On the other hand, we have also observed the reduction of carrier mobility in a thinner strained-Si layer or at higher vertical electric field conditions. For the first time, we have demonstrated a high-speed CMOS ring-oscillator using strained-SOI devices, and its improvement amounts to 63% at the supply voltage of 1.5 V, compared to control-SOI CMOS.

SOI technology for the GHz era

Silicon-on-insulator (SOI) CMOS offers a 20–35% performance gain over bulk CMOS. High-performance microprocessors using SOI CMOS have been commercially available since 1998. As the technology moves to the 0.13-µm generation, SOI is being used by more companies, and its application is spreading to lower-end microprocessors and SRAMs. In this paper, after giving a short history of SOI in IBM, we describe the reasons for performance improvement with SOI, and its scalability to the 0.1-µm generation and beyond. Some of the recent applications of SOI in high-end microprocessors and its upcoming uses in low-power, radio-frequency (rf) CMOS, embedded DRAM (EDRAM), and the integration of vertical SiGe bipolar devices on SOI are described. As we move to the 0.1-µm generation and beyond, SOI is expected to be the technology of choice for system-on-a-chip applications which require high-performance CMOS, low-power, embedded memory, and bipolar devices.

On the high-performance Ti-salicide ULSI CMOS devices prepared by a borderless contact technique and double-implant structure

A borderless contact (BLC) technique and double-implant structure (DIS) have been developed successfully to fabricate high-performance Ti-salicide sub-quarter-micron CMOS devices. A SiOxNy film grown by low-temperature chemical vapour deposition is used to act as the selective etch-stop layer. The n+ and p+ DIS can reduce the junction leakage current which is usually enhanced by BLC etching near the edge of shallow trench isolation. Based on the use of the BLC process, the process window can be enlarged. In addition, the employed low-thermal oxynitride and high deposition rate can improve the salicide thermal stability and avoid the salicide agglomeration. Experimentally, by combining the BLC and DIS techniques, low leakage and low sheet resistance CMOS devices and low standby current and high yield 1 Mb SRAMs are fabricated successfully.

An 0.18-μm CMOS for mixed digital and analog applications with zero-volt-V/sub th/ epitaxial-channel MOSFETs

An 0.18-/spl mu/m CMOS technology with multi-V/sub th/s for mixed high-speed digital and RF-analog applications has been developed. The V/sub th/s of MOSFETs for digital circuits are 0.4 V for NMOS and -0.4 V for PMOS, respectively. In addition, there are n-MOSFET's with zero-volt-V/sub th/ for RF analog circuits. The zero-volt-V/sub th/ MOSFETs were made by using undoped epitaxial layer for the channel regions. Though the epitaxial film was grown by reduced pressure chemical vapor deposition (RP-CVD) at 750/spl deg/C, the film quality is as good as the bulk silicon because high pre-heating temperature (940/spl deg/C for 30 s) is used in H/sub 2/ atmosphere before the epitaxial growth. The epitaxial channel MOSFET shows higher peak g/sub m/ and f/sub T/ values than those of bulk cases. Furthermore, the g/sub m/ and f/sub T/ values of the epitaxial channel MOSFET show significantly improved performances under the lower supply voltage compared with those of bulk. This is very important for RF analog application for low supply voltage. The undoped-epitaxial-channel MOSFETs with zero-V/sub th/ will become a key to realize high-performance and low-power CMOS devices for mixed digital and RF-analog applications.

Self-aligned Ti and Co silicides for high performance sub-0.18 μm CMOS technologies

An overview of the development of advanced Ti and Co self-aligned silicide (SALICIDE) processes for deep-sub micron high performance CMOS technologies at Texas Instruments is presented. SALICIDES are a key factor for scaling of high-performance CMOS devices. They are used to lower sheet resistance of gate and source/drain regions, contact resistance and source/drain series resistance, increasing device performance and lowering RC delays to allow faster operation. Their applicability to deep-sub-micron technologies is determined by the fundamental materials aspects controlling silicide phase formation and evolution, as well as process integration issues such as effect of subsequent processing steps on the silicide films or effects of silicide related process steps on transistor characteristics. The main scaling issues for conventional processes, high resistivity on narrow lines for Ti SALICIDE and high diode leakage on shallow junctions for Co SALICIDE, are addressed. Detailed kinetic studies of the high resistivity to low resistivity phase transformations (TiSi 2 C49 to C54 and CoSi to CoSi 2) and their dependence on linewidth and film thickness are presented. A nucleation density model is shown to account for the measured linewidth dependence and effect of pre-amorphization implants on the TiSi 2 C49 to C54 transformation and explain, as a result, narrow line sheet resistance. This overview covers studies on rapid thermal processing (RTP) for Ti and for Co SALICIDE, pre-amorphization implants and Mo impurities which allowed the first demonstration of low resistivity Ti SALICIDE at 0.10 μm gate lengths, as well as applications to sub-0.18 μm CMOS technologies and integration issues.

Monolithic Fabrication of Flexible Film and Thinned Integrated Circuits

A new monolithic device technology for micromachines has been developed. This device consists of a flexible film and thinned integrated circuits. The fabrication process is compatible with high performance CMOS devices. The flexible film includes high density wires and other electric functions in several micrometers thick. The integrated circuits are thinned by electrochemical etching to less than 20μm thick. This device is useful for integration and size reduction of electric components for micromachines. We have fabricated the monolithic devices and investigated the characteristics.

Electrical packaging requirements for low-voltage ICs—3.3 V high-performance CMOS devices as a case study : Ramesh Senthinathan, Arun Mehra, Mali Mahalingham, Yutaka Doi and Hector Astrain. IEEE Transactions on Components, Packaging, and Manufacturing Technology—Part B, 17, 4, 493 (November 1994)

Electrical packaging requirements for low-voltage ICs—3.3 V high-performance CMOS devices as a case study : Ramesh Senthinathan, Arun Mehra, Mali Mahalingham, Yutaka Doi and Hector Astrain. IEEE Transactions on Components, Packaging, and Manufacturing Technology—Part B, 17, 4, 493 (November 1994)

Electrical packaging requirements for low-voltage ICs-3.3 V high-performance CMOS devices as a case study

Motivated by reduced-power dissipation and increased demand for portable systems, supply voltage for ICs is scaled down from present 5 V. However, packaging these reduced supply voltage devices demands closer attention to electrical packaging requirements. This work focuses on high-performance CMOS device technology for 5 V and 3.3 V operations. Devices are housed in quad flat (QFP), ball grid array (BGA), and pin grid array (PGA) packages. Maintaining computational throughput (CTP) introduces comparable noise levels for 5 V and 3.3 V operations. This increases the probability of false switching in 3.3 V operation. Noise levels for lesser, comparable, and faster CTP 3.3 V packaged devices are given. False switching for 3.3 V operation is analyzed using receiver dynamic noise immunity. Packaged device performance and noise were measured to validate the modeling and simulation methodology, and general trends. "What if" study was performed to reduce simultaneous switching noise (SSN) using various techniques and their merits are explained.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

High-performance salicide shallow-junction CMOS devices for submicrometer VLSI application in twin-tub VI

A 3.3-V CMOS technology with 0.6- mu m design rules in sixth-generation twin-tub CMOS (twin-tub VI) was developed. The major features of the device in this technology are: HIPOX twin-tub structure, n/sup +//p/sup +/ dual-type poly gate, 125-AA thin gate oxide, shallow junctions, rapid thermal anneal activation, and thin TiSi/sub 2/ as the source/drain/gate silicide layer. Electrical measurements show good I-V characteristics, ideal low junction leakage, latchup immunity for 4.5- mu m n/sup +/-to-p/sup +/ spacing, more than 6.0-V NMOSFET snapback breakdown voltage, good hot-carrier aging properties, and undetectable dopant interlateral diffusion through a TiSi/sub 2/ shunt layer of a different type of poly. The transistors were scaled to 0.45- and 0.40- mu m effective channel length without punchthrough at V/sub ds/=3.6 V for NMOS and PMOS, respectively. A 100-ps stage delay was obtained on a 101-stage CMOS ring oscillator at an operating voltage of 3.3 V. >

Recent advances in solid-phase epitaxial recrystallization of SOS with applications to CMOS and bipolar devices

Recent advances in solid-phase epitaxial recrystallization suggest that this technology may dramatically improve the crystallinity of heteroepitaxial silicon-on-insulators, such as silicon-on-sapphire (SOS). Recent improvements of 0.3- and 0.5-μm SOS films using two solid-phase epitaxial recrystallization processes (SPEAR and DSPE) are reported. Both techniques have reduced the total microtwin densities of SOS samples by more than 100-fold, while increasing electron and hole mobilities approximately 50%. The resulting properties are very close to those of bulk silicon. High-performance submicrometer CMOS devices and circuits in 0.3-μm recrystallized SOS films have been fabricated.

Selective LPCVD Tungsten for Contact Barrier Applications

This study assesses the use of selective LPCVD tungsten as a contact barrier in VLSI circuits. Measurements of the contact resistance and leakage current are evaluated as a function of variations in W deposition parameters, implant type, implant dosage, and metallization heat‐treatment. Addition of to alter the equilibrium of the displacement reaction is seen to cause minimal erosion and encroachment of the Si contacts as well as produce low and thermally stable contact resistances to both n+ and p+ diffusions. For surface doping concentrations of and , measured values of the contact resistance for 2.0 μm sized vias are near 30Ω. Such values are quite compatible with high performance CMOS device requirements. Further reductions in these values are achieved with use of a self‐aligned contact barrier metallization. The contact resistance for 2.0 μm sized vias are, in this case, near 4 and 15OHgr; for the n+ and p+diffusions, respectively. Sporadic leakage across shallow n+/P‐Tub junctions remains, however, a serious problem associated with this selective LPCVD W process. Understanding the origin of this leakage and eliminating it can lead to numerous applications of this technology in VLSI manufacturing.

Low 1/f noise design of Hi-CMOS devices

Low-frequency noise characteristics of High-Performance CMOS(Hi-CMOS) devices were measured. It was found that the equivalent input noise power S Vg,eq for n-channel MOSFET's has a 1/fα spectrum (0.8 G of 2 µm. The S Vg,eq is clearly proportional to 1/L eff down to 0.8 µm. The noise characteristics of p-channel and n-channel MOSFET's were compared. It was found that in Hi-CMOS devices, noise reduction in normally-off-type p-channel devices was obtained by light boron-ion implantations at doses below 1012cm-2. The 1/f noise level of p-channel devices was reduced to 1/10- 1/20 that of n-channel devices. In n-channel devices, the low-frequency noise power is a slow increasing function of the drain current. In p-channel devices, on the other hand, a threshold current was observed at which the noise begins to increase rapidly. The results are discussed in this paper in relation to the theoretical model of 1/f noise. The device design for reducing 1/f noise in CMOS differential amplifiers is also examined.