High-performance Clock Research Articles

Source Switched Charge-Pump PLLs for High-Dose Radiation Environments

This paper presents a radiation tolerant charge-pump Phase-Locked Loop (PLL) with low static phase error variability suitable for high-performance clock systems in high-dose radiation environments. We investigate the use of source switching charge-pump architectures to minimize any voltage-or dose-dependent charge injection and address the limitations of Enclosed Layout Transistors (ELTs) in the conventional drain switched charge-pump. The circuit has been processed in a 65nm Complementary Metal Oxide Semiconductor (CMOS) technology and has been experimentally verified with X-rays up to a total ionizing dose of 180 Mrad.

Performance Investigation on a Clock Distribution and Synchronization Scheme Over DWDM Optical Links

For most large-scale physics experiments, it is desirable that the clock distribution and data transmission are unified on a single optical network. To meet the requirement of current large-scale physics experiments for clock synchronization accuracy in the range of tens of picoseconds, and adapt to the increasingly widespread use of dense wavelength division multiplexing (DWDM) optics, this paper investigates the performance of clock distribution and synchronization scheme based on DWDM optics and high-speed serializer-deserializer (SerDes) transceivers embedded in field programmable gate arrays (FPGAs). By extending our previously proposed simplified calibration procedure based on the White Rabbit protocol to the present asymmetric link, all possible errors, especially the new factors brought about by the asymmetric link, are investigated so that the time uncertainty on the link can be minimized. Using the built test system to carry out multiple Reset and long-term operation tests, the measured clock synchronization accuracy over a 5km optical fiber connection is better than 20ps, and the RMS jitter of the recovered clock is less than 10ps. The test results show that the combination of White Rabbit with DWDM optics can have both high-bandwidth data transmission and high-performance clock synchronization at the same time.

Designing digital circuits based on quantum-dots cellular automata using nature-inspired metaheuristic algorithms: A systematic literature review

Quantum-dot Cellular Automata (QCA) is prospective nanotechnology that has been named one of the top six upcoming computer technologies. QCA is a method for building computational systems that encode binary logics via the arrangement of charges among quantum dots. It is highly fast, has low power usage, and is extremely dense. QCA technology, in particular, brings up new possibilities for power savings and high-performance clock rates. Because of the appropriate properties, the execution of logic circuits utilizing QCA technology is a hotly debated topic. Design tools must handle many problems posed by QCA technology circuit design. Nature-inspired meta-heuristic algorithms play a vital role in computer processing, and algorithms with faster performance rates are more valuable. However, so far, there is no systematic study that regularly examines the role of nature-inspired met heuristic algorithms in QCA. Hence, the present investigation examines the applications of nature-inspired met heuristic algorithms in QCA. The articles on QCA optimization algorithms are selected and analyzed using the systematic literature review method. Also, important challenges and suggestions for future work are highlighted. The results showed that QCA-based digital logic circuits could be optimized using nature-inspired algorithms by reducing the number of gates.

Radium Ion Optical Clock.

We report the first operation of a Ra^{+} optical clock, a promising high-performance clock candidate. The clock uses a single trapped ^{226}Ra^{+} ion and operates on the 7s ^{2}S_{1/2}→6d ^{2}D_{5/2} electric quadrupole transition. By self-referencing three pairs of symmetric Zeeman transitions, we demonstrate a frequency instability of 1.1×10^{-13}/sqrt[τ], where τ is the averaging time in seconds. The total systematic uncertainty is evaluated to be Δν/ν=9×10^{-16}. Using the clock, we realize the first measurement of the ratio of the D_{5/2} state to the S_{1/2} state Landé g-factors: g_{D}/g_{S}=0.598 805 3(11). A Ra^{+} optical clock could improve limits on the time variation of the fine structure constant, α[over ˙]/α, in an optical frequency comparison. The ion also has several features that make it a suitable system for a transportable optical clock.

ACES/PHARAO: high-performance space-to-ground and ground-to-ground clock comparison for fundamental physics

The Atomic Clock Ensemble in Space is a fundamental physics mission of the European Space Agency to be launched in August 2021. It relies on a high-performance clock onboard the International Space Station (ISS), a network of high-performance clocks on ground, a dedicated 2-way microwave link (MWL) enabling space-to-ground and ground-to-ground clock comparisons, as well as an optical link (ELT). PHARAO/SHM (Projet d’Horloge Atomique par Refroidissement d’Atomes en Orbite/Space Hydrogen Maser), the clock onboard the ISS, has a relative frequency accuracy at the \({10}^{-16}\) level, a relative frequency stability (Allan deviation) equal to \({10}^{-13}/\sqrt{\tau }\) (\(\tau\) being the integration time in seconds) and a time deviation of 12 picoseconds after one day of integration. The MWL is designed to reach a time deviation below 7 ps after one day of integration. While space-to-ground clock comparisons will enable precise tests of the gravitational redshift, tests of deviations from General Relativity at the \({10}^{-6}\) level, and tests of local Lorentz invariance at the \({10}^{-10}\) level, ground-to-ground clock comparisons will enable a search of the time variation of fundamental constants with uncertainty at the \({10}^{-17}\) level after one year. In this contribution, we review the mission setup with a particular emphasis on the MWL, discuss the simulation and data analysis software developed to investigate mission performance, focusing on its primary scientific objective: the test of the gravitational redshift.

STFL-DDR: Improving the Energy-Efficiency of Memory Interface

Power dissipation is a significant problem limiting the performance of today's computer systems. One of the main contributors to power consumption in microprocessors is data movement in cache and memory interface. Several solutions such as low power interconnects, energy-aware data encoding, and low power signaling have been proposed to mitigate this problem. Almost all of these techniques result in a significant system performance degradation. This article examines the application of a novel technique, called STFL-DDR, for hybrid signaling on low-power DRAM interface. To keep the power consumption low, STFL-DDR employs a high-performance clock rate for transferring data on low power wires. To avoid any signal deterioration, STFL-DDR employs data encoding/decoding to prevent each wire from switching in any two consecutive cycles. STFL-DDR creates new opportunities for optimizing the energy-efficiency of DRAM systems. We compare the efficiency of STFL-DDR with the state-of-the-art methods by simulating a mix of 12 parallel benchmark applications on a muticore system. Our simulation results indicate that STFL can reduce the energy consumption of a contemporary DRAM interface by 17 percent as compared to an LPDDR baseline while achieving the throughput of a high-performance DRAM. Applying STFL to both last level cache and DRAM interface results in improving the system energy, energy-delay product, and performance by 8, 15, and 9 percent respectively. Compared with a high-performance memory interface, STFL improves the system energy and energy-delay product by 25 and 75 percent, while reaching 98 percent of the average performance of the high-performance system.

A Fine-Tuned Positioning Algorithm for Space-Borne GNSS Timing Receivers.

To maximize the usage of limited transmission power and wireless spectrum, more communication satellites are adopting precise space–ground beam-forming, which poses a rigorous positioning and timing requirement of the satellite. To fulfill this requirement, a space-borne global navigation satellite system (GNSS) timing receiver with a disciplined high-performance clock is preferable. The space-borne GNSS timing receiver moves with the satellite, in contrast to its stationary counterpart on ground, making it tricky in its positioning algorithm design. Despite abundant existing positioning algorithms, there is a lack of dedicated work that systematically describes the delicate aspects of a space-borne GNSS timing receiver. Based on the experimental work of the LING QIAO (NORAD ID:40136) communication satellite’s GNSS receiver, we propose a fine-tuned positioning algorithm for space-borne GNSS timing receivers. Specifically, the proposed algorithm includes: (1) a filtering architecture that separates the estimation of satellite position and velocity from other unknowns, which allows for a first estimation of satellite position and velocity incorporating any variation of orbit dynamics; (2) a two-threshold robust cubature Kalman filter to counteract the adverse influence of measurement outliers on positioning quality; (3) Reynolds averaging inspired clock and frequency error estimation. Hardware emulation test results show that the proposed algorithm has a performance with a 3D positioning RMS error of 1.2 m, 3D velocity RMS error of 0.02 m/s and a pulse per second (PPS) RMS error of 11.8ns. Simulations with MATLAB show that it can effectively detect and dispose outliers, and further on outperforms other algorithms in comparison.

Dual-cell structure digitally controlled oscillator with portability for clock generation applications.

This paper presents a dual-cell structure and cell-based design digitally controlled oscillator (DCO) for high-performance clock generation applications. The proposed dual-cell DCO not only can reduce the intrinsic delay to increase the maximum output frequency significantly but also extend the controllable range. In addition, the proposed digitally controlled delay cell uses the cascading structure to realize the wide output frequency range and high timing resolution at the same time. A DCO chip is fabricated in 0.18 µm CMOS technology, and the core area is 0.003 mm2. Measurement results show that operation range is from 169 MHz to 522 MHz and the finest delay resolution is 2.2 ps. Furthermore, because the proposed DCO is implemented with the digital standard cells, it is a portable design to migrate to different processes easily and reduce design time significantly.

HCDN: Hybrid-Mode Clock Distribution Networks

We propose a new hybrid clock distribution scheme that uses global current-mode and local voltage-mode (VM) clocking to distribute a high-performance clock signal with reduced power consumption. In order to enable hybrid clocking, we propose two new current-to-voltage converters. The converters are simple current receiver circuits based on amplifier and current-mirror circuits. The global clocking is bufferless and relies on current rather than voltage, which reduces the jitter. The local VM network improves compatibility with traditional CMOS logic. The hybrid clock distribution network exhibits 29% lower average power and 54% lower jitter-induced skew in a symmetric network compared to traditional VM clocks. To use hybrid clocking efficiently, we present a methodology to identify the optimal cluster size and the number of required receiver circuits, which we demonstrate using the ISPD 2009, ISPD 2010, and ISCAS89 testbench networks. At 1–2-GHz clock frequency, the proposed methodology uses up to 45% and 42% lower power compared to a synthesized buffered VM scheme using ISPD 2009 and ISPD 2010 testbenches, respectively. In addition, the proposed hybrid clocking scheme saves up to 50% and 59% of power compared to a buffered scheme using the ISCAS89 benchmark circuit at 1- and 2-GHz clock frequency, respectively.

A 0.009 mm2 Wide-Tuning Range Automatically Placed-and-Routed ADPLL in 14-nm FinFET CMOS

An automatically placed-and-routed all-digital PLL for high-performance clock generation and distribution in many-core processors is presented. The proposed design leverages a phase domain architecture, and features an embedded TDC constructed from standard cells. TDC resolution is enhanced through the use of a phase interpolator. The standard cell library is extended with custom oscillator cells are designed to achieve optimized power, performance, and area. Timing and handling of potentially metastable paths is additionally handled by the digital design flow. The clock generator has been fabricated in a 14-nm FinFET process, and occupies an area of 0.009 mm2. The design features a tuning range from 1.0 to 5.5 GHz (80%). Output period jitter of 1.29 ps is achieved with a power consumption of 9.7 mW.

A Multiobjective Cooptimization of Buffer and Wire Sizes in High-Performance Clock Trees

Clock buffer and wire sizing are intertwined problems that also greatly impact power consumption and skew in clock trees. Due to their complexity, they are often solved separately, leading to suboptimal solutions. In this brief, we propose a new formulation for cooptimization of buffer and wire sizes for high-performance clock trees. Using the proposed cooptimization of buffer and wire sizes, we are able to minimize a combination of both power and skew. The variation-aware experiments show that, by applying the proposed formulation, power and skew for all tested clock trees are improved. On average, we achieve a reduction of 57% in power and 50 ps in skew. We also show that our solutions are Pareto optimal where power and skew cannot be further reduced simultaneously and they provide a balanced tradeoff between power and skew.

Transfer cavity scheme for stabilization of lattice laser in ytterbium lattice clock

For high performance clock, optical lattice is introduced to generate periodic trap for capturing neutral atoms through weak interactions. However, the strong trapping potential can bring a large AC Stark frequency shift due to imbalance shifts for the upper and lower energy levels of the clock transition. Fortunately, it is possible to find a specific “magic” wavelength for the lattice light, at which the first-order net AC Stark shift equals zero. To achieve high stability and accuracy of a neutral atomic optical clock, the frequency of the lattice laser must be stabilized and controlled to a certain level around magic wavelength to reduce this shift.#br#In this paper, we report that the frequency of lattice laser is stabilized and linewidth is controlled below 1 MHz with transfer cavity scheme for ytterbium (Yb) clock. A confocal invar transfer cavity mounted in an aluminum chamber is locked through the Pound-Drever-Hall (PDH) method to a 780 nm diode laser stabilized with modulation transfer spectroscopy of rubidium D2 transition. It is then used as the locking reference for the lattice laser. This cavity has a free spectral range of 375 MHz, as well as fineness of 236 at 780 nm, and 341 at 759 nm. Because neither of the wavelengths of 759 nm and 780 nm is separated enough to use optical filter, they are coupled into the cavity with transmission and reflection way respectively, and the two PDH modulation frequencies are chosen differently to avoid possible interference.#br#The stabilization of the 759 nm lattice laser on transfer cavity can stay on for over 12 hours without escaping or mode hopping. To estimate the locking performance of the system, a beat note with a hydrogen maser-locked optical frequency comb is recorded through a frequency counter at 10 ms gate time for over 3 hours. This beat note shows that the frequency fluctuation is in a range of 10 kHz corresponding to a stability of 2×10-11 level with 0.1 s averaging time, but goes up to 150 kHz corresponding to a stability of 3.6×10-10 at 164 s averaging time. The long-term drift can be the result of air pressure fluctuation on the transfer cavity, or the bad stability of the optical comb in the measurement process. However, current locking performance is still enough for the requirement of 10-17 clock uncertainty.#br#In conclusion, we succeed in realizing frequency stabilization and control for the lattice laser of Yb clock with the transfer cavity scheme. The result shows that the short-term stability is around 10-11 level, though a mid-long-term drift exists. However, the stability of 3.6×10-10 over 164 s can still promise a 10-17 uncertainty for the Yb clock. And, it can be reduced if the averaging time is long enough. The work can be further improved by installing the transfer cavity into vacuum housing for better stability in future.

An all-digital semi-blind clock and data recovery system

This paper presents a digitally intensive semi-blind clock and data recovery (SBCDR) system. The paper covers the theory, analysis, and system level simulation of this SBCDR. The proposed CDR is tailored to target the optical network standard OC-192. The SBCDR can provide the required jitter tolerance (JTo), and still provide enough jitter filtering to achieve the jitter transfer (JTr) requirements. Also, the recovered clock achieves a low jitter generation (JG) of 0.01 UIrms and 0.0064 UIrms for both the wide-band and high-band jitter filters defined by the standard. The proposed SBCDR provides two advantages over typical SBCDRs and PLL-based CRDs that target OC-192. First, the digitally intensive nature provides a scalable and process tolerant design. Second, the architecture provides a CDR that can pass all three jitter performance metrics, without the aid of an external clean-up phase locked loop (PLL) or a high performance clock multiplication unit (CMU) typically required by OC-192 transceivers. By utilizing a circular representation for the phase calculation in the over-sampling clock and data recovery (OSCDR), extensive pipe-lining in the implementation and higher data rate tolerance can be achieved. The simulation results of the proposed SBCRD agree closely with theoretical results.

A Design for Clock Synchronization Using CPPLL

High performance clock synchronization system is essential in communication transmission, which is based on the principle of phase locked loop synchronization that tracking a high accuracy, high stability reference clock source usinh low-pass filter to turn the value into voltage and to control VCO or VXCO and makes the output frequency and the input frequency to maintain strict synchronization.

Revisiting automated physical synthesis of high-performance clock networks

High-performance clock distribution has been a challenge for nearly three decades. During this time, clock synthesis tools and algorithms have strove to address a myriad of important issues helping designers to create faster, more reliable, and more power efficient chips. This work provides a complete discussion of the high-performance ASIC clock distribution using information gathered from both leading industrial clock designers and previous research publications. While many techniques are only briefly explained, the references summarize the most influential papers on a variety of topics for more in-depth investigation. This article also provides a thorough discussion of current issues in clock synthesis and concludes with insight into future research and design challenges for the community at large.

High-performance and Low-power Clock Branch Sharing Pseudo-NMOS Level Converting Flip-flop

High-performance and Low-power Clock Branch Sharing Pseudo-NMOS Level Converting Flip-flop

High-performance clock mesh optimization

Clock meshes are extremely effective at producing low-skew regional clock networks that are tolerant of environmental and process variations. For this reason, clock meshes are used in most high-performance designs, but this robustness consumes significant power. In this work, we present two techniques to optimize high-performance clock meshes. The first technique is a mesh perturbation methodology for nonuniform mesh routing. The second technique is a skew-aware buffer placement through iterative buffer deletion. We demonstrate how these optimizations can achieve significant power reductions and a near elimination of short-circuit power. In addition, the total wire length is decreased, the number of required buffers is decreased, and both skew and robustness are improved on average when variation is considered.

An Effective and Efficient Framework for Clock Latency Range Aware Clock Network Synthesis

In this paper, we present an effective and efficient framework to minimize clock latency range (CLR), which is a crucial objective measuring the process variability of the high-performance clock network. An enhanced deferred-merge embedding algorithm is proposed to handle the skew and slew constraints simultaneously. Besides, instead of using traditional buffering methods that consider only capacitance loading, we adopt slew-constrained buffering for more accurate results. To explore the variation effect with different combinations of buffers and wires in terms of CLR, we design an experiment to examine it and propose an effective buffer and wire sizing scheme. In addition, obstacle avoidance handling is included in our framework. Experimental results show that our framework achieves the best results in terms of CLR compared with any other team in the 2009 ACM ISPD clock network synthesis contest and four state-of-the-art works.

Osciladores Controlados por Voltaje para la Generación y Distribución Simultánea de Señal de Reloj en Sistemas en Chip

Actualmente el diseno de sistemas de generacion y distribucion de senal/es de reloj de alto desempeno (alta frecuencia, skew, jitter y consumo de potencia reducidos) para sistemas en un Solo Chip (SoC), constituye una importante area de investigacion en el desarrollo de sistemas electronicos. En este articulo se presenta un analisis de las principales filosofias de diseno de redes de generacion y distribucion de senal de reloj actuales y futuras. Se deriva que las redes no-resonantes en base a osciladores controlados por voltaje/corriente representan una alternativa altamente atractiva para la sincronizacion de sistemas en un solo chip debido a su facil diseno, alta regularidad, y escalabilidad con la tecnologia de fabricacion.

Design methodology for synthesizing clock distribution networks exploiting nonzero localized clock skew

An integrated top-down design methodology is presented in this brief for synthesizing high performance clock distribution networks based on application dependent localized clock skew. The methodology is divided into four phases: (1) determining an optimal clock skew schedule composed of a set of nonzero clock skew values and the related minimum clock path delays; (2) designing the topology of the clock distribution network with delays assigned to each branch based on the circuit hierarchy, the aforementioned clock skew schedule, and minimizing process and environmental delay variations; (3) designing circuit structures to emulate the delay values assigned to the individual branches of the clock tree; and (4) designing the physical layout of the clock distribution network. The clock distribution network synthesis methodology is based on CMOS technology. The clock lines are transformed from distributed resistive capacitive interconnect lines into purely capacitive interconnect lines by partitioning the RC interconnect lines with inverting repeaters. Variations in process parameters are considered during the circuit design of the clock distribution network to guarantee a race-free circuit. Nominal errors of less than 2.5% for the delay of the clock paths and 7% for the clock skew between any two registers belonging to the same global data path as compared with SPICE Level-3 are demonstrated.