High Performance Charge Pump Research Articles

High-Performance Charge Pump Regulator with Integrated CMOS Voltage Sensing Control Circuit

This paper introduces a design for a charge pump DC-DC boost regulator with an integrated low-voltage control circuit. With a charge pump and feedback circuits implemented in 0.35 µm CMOS technology, the proposed DC-DC boost regulator offers an efficient device solution for low-power applications. The proposed design employs an error amplifier, oscillator, and comparator in the control circuit which is designed with a supply voltage of 1.8–3.5 V and 2 MHz frequency. Stability is obtained via a pole-zero compensation in the feedback circuit. The charge pump regulator with four pump stages and the whole regulator circuit are analyzed using the Cadence simulation tool. Measurements of the fabricated 0.35 µm CMOS regulator show that the transient time of the error amplifier is controlled within 1.0 µsec and the output voltage is accurately controlled from 7.8 V to 9.4 V with 27–38 mV ripple and 4.5 mA maximum current.

A High-Performance Charge Pump Topology for Very-Low-Voltage Applications

This brief presents a novel charge pump suitable to work under very-low-voltage supply. The circuit exploits a novel charge transfer switch made up by the combination of a NMOS and a PMOS transistor whose gates are connected to internal nodes of the charge pump to enhance overdrive voltage. This solution allows working with supply voltage values lower that the MOS threshold voltage. Post layout simulation results using a 65-nm CMOS standard technology show the effectiveness of the proposed solution and its advantage as compared to a traditional latched charge pump in terms of high current driving range, power efficiency and speed.

A simple and high performance charge pump based on the self-cascode transistor

A novel charge pump for phase locked loops application based on the self-cascode (SC) transistor is presented. The proposed charge pump is simple and adds just a few number of transistors to basic charge pump circuit. The SC transistor is self-biased and has high output impedance and lower voltage headroom. Threshold voltage reduction method is used in SC transistor to reduce transistor size, increase the output resistance and help to improve the self-biased structure. The post layout simulation for the charge pump with SC transistor is performed using 180 nm CMOS technology. Based on the Monte Carlo process variation and corner case simulation a 2% current mismatch over the voltage range of 0.35–1.48 V is observed.

Analysis and Design of High Performance Phase Frequency Detector, Charge Pump and Loop Filter Circuits for Phase Locked Loop in Wireless Applications

<p>This paper presents the analysis and design of high performance phase frequency detector, charge pump and loop filter circuits for phase locked loop in wireless applications. The proposed phase frequency detector (PFD) consumes only 8 µW and utilises small area. Also, at 1.8V voltage supply the maximum operation frequency of the conventional PFD is 500 MHz whereas proposed PFD is 5 GHz. Hence, highly suitable for low power, high speed and low jitter applications. The differential charge pump uses switches using NMOS and the inverter delays for up and down signals do not generate any offset due to its fully symmetric operation. This configuration doubles the range of output voltage compliance compared to single ended charge pump. Differential stage is less sensitive to the leakage current since leakage current behaves as common mode offset with the dual output stages. All the circuits are implemented using cadence 0.18 μm CMOS Process.</p>

A power management system for energy harvesting and wireless sensor networks application based on a novel charge pump circuit

ABSTRACTEnergy Harvesting circuits are developed as an alternative solution to supply energy to autonomous sensor nodes in Wireless Sensor Networks. In this context, this paper presents a micro-power management system for multi energy sources based on a novel design of charge pump circuit to allow the total autonomy of self-powered sensors. This work proposes a low-voltage and high performance charge pump (CP) suitable for implementation in standard complementary metal oxide semiconductor (CMOS) technologies. The CP design was implemented using Cadence Virtuoso with AMS 0.35μm CMOS technology parameters. Its active area is 0.112 mm2. Consistent results were obtained between the measured findings of the chip testing and the simulation results. The circuit can operate with an 800 mV supply and generate a boosted output voltage of 2.835 V with 1 MHz as frequency.

High Performance Charge Pump Converter with Integrated CMOS Feedback Circuit

In this paper, an integrated low-voltage control circuit is introduced for a charge pump DC-DC boost converter. By exploiting the advantage of the integration of the feedback control circuit within CMOS technology, the charge pump boost converter offers a low-current operation with small ripple voltage. The error amplifier, comparator, and oscillator in the control circuit are designed with the supply voltage of 3.3 V and the operating frequency of 1.6~5.5 MHz. The charge pump converter with the 4 or 8 pump stages is measured in simulation. The test in the <TEX>$0.35{\mu}m$</TEX> CMOS process shows that the load current and ripple ratio are controlled under 1 mA and 2% respectively. The output-voltage is obtained from 4.8 ~ 8.5 V with the supply voltage of 3.3 V.

A Supply-Noise-Insensitive PLL in Monolithic Active Pixel Sensors

A high-performance CMOS charge pump supply-noise-insensitive phase-locked loop (SNI-PLL) for on-chip clock generation of Monolithic Active Pixel Sensors (MAPS) is presented. The SNI-PLL employs a voltage regulator which provides two stable power supplies to the charge pump and the voltage-controlled oscillator (VCO), respectively. The voltage regulator achieves a Power Supply Noise Rejection (PSNR) of -40 dB over the entire frequency spectrum by using virtual grounded cascode compensation technique. The presented SNI-PLL generates a 160 MHz clock with a Time Interval Error (TIE) of 0.062 UI (Unit Interval) from a 10 MHz reference clock in a noisy power supply environment. The circuit was fabricated with a 0.35 μ m standard CMOS process and occupies 0.38 mm 2 area. The power consumption of the SNI-PLL is about 15.2 mW at 160 MHz.

Design of a high performance CMOS charge pump for phase-locked loop synthesizers

A new high performance charge pump circuit is designed and realized in 0.18 μm CMOS process. A wide input ranged rail-to-rail operational amplifier and self-biasing cascode current mirror are used to enable the charge pump current to be well matched in a wide output voltage range. Furthermore, a method of adding a precharging current source is proposed to increase the initial charge current, which will speed up the settling time of CPPLLs. Test results show that the current mismatching can be less than 0.4% in the output voltage range of 0.4 to 1.7 V, with a charge pump current of 100 μA and a precharging current of 70 μA. The average power consumption of the charge pump in the locked condition is around 0.9 mW under a 1.8 V supply voltage.

Design of High Gain, High Bandwidth Op-Amp for Reduction of Mismatch Currents in Charge Pump PLL in 180 nm CMOS Technology

The designing of charge pump with high gain OpAmp is a challenging task for getting faithful response .Design of high performance phase locked loop require ,a design of high performance charge pump .We have designed a operational amplifier for reducing the error caused by high speed glitch in a transistor and mismatch currents . A separate Op-Amp has designed in 180 nm CMOS technology by CADENCE VIRTUOSO tool. This paper describes the design of high performance charge pump for GHz CMOS PLL targeting orthogonal frequency division multiplexing (OFDM) application. A high speed low power consumption Op-Amp with more than 500 MHz bandwidth has designed for increasing the speed of charge pump in Phase locked loop. Keywords—Charge pump (CP) Orthogonal frequency division multiplexing (OFDM),Phase locked loop (PLL), Phase frequency detector (PFD), Voltage controlled oscillator (VCO),

Charge Pump Circuits for Low‐voltage Applications

In this paper, a low‐voltage, high performance charge pump circuit, suitable for implementation in standard CMOS technologies is proposed. Its pumping operation is based on cascading several cross‐connected NMOS voltage doubler stages. For very low‐voltage applications (1.2 V, 0.9 V), where the performance of the NMOS transistors is limited due to body effect, two improved versions of the charge pump with cascaded voltage doublers (charge pump with CVD) are also proposed. The first utilises PMOS transistors (charge pump with CVD‐PMOS) in parallel to the cross‐connected NMOS transistors, while the second improves the pumping gain by boosting the clock amplitude (charge pump with CVD‐BCLK). Simulations at 50 MHz have shown that a five‐stages charge pump with CVD can achieve a 1.5–8.4 V voltage conversion. For the same stage number and frequency, an output voltage of 4 and 7.3 V can be generated from 0.9 V, by using the charge pump with CVD‐PMOS and the charge pump with CVD‐BCLK, respectively.