High-performance Carbon Nanotube Thin-film Transistors Research Articles

Controllable etching-induced contact enhancement for high-performance carbon nanotube thin-film transistors.

Semiconducting single-walled carbon nanotubes (s-SWNTs) show great promises in advanced electronics. However, contact resistance between the nanotubes and metal electrode has long been a bottleneck to the development of s-SWNTs in high-performance electronic devices. Here we demonstrate a simple and controllable strategy for enhancing the electrode contact and therefore the performance of s-SWNT thin film transistors by plasma etching treatment, which effectively removes the polymer residues, including the photoresist and the conjugated molecules, adsorbed on the surface of s-SWNTs. As a result, the contact resistance is reduced by 3 times and the carrier mobility rises by up to 70%. Our method is compatible with current silicon semiconductor processing technology, making it a viable effective approach to large-scale application of s-SWNTs in the electronics industry.

Large-area and highly uniform carbon nanotube film for high-performance thin film transistors

Carbon nanotube thin film transistors (CNT-TFTs) are a potential TFT technology for future high-performance macroelectronics. Practical application of CNT-TFTs requires the production of large-area, highly uniform, density-controllable, repeatable, and high-throughput CNT thin films. In this study, CNT films were fabricated on 4-inch Si wafers and 2.5th generation (G2.5) backplane glasses (370 mm × 470 mm) by dip coating using a chloroform-dispersed high-purity semiconducting CNT solution. The CNT density was controlled by the solution concentration and coating times, but was almost independent of the substrate lifting speed (1–450 mm·min−1), which enables high-throughput CNT thin film production. We developed an image processing software to efficiently characterize the density and uniformity of the large-area CNT films. Using the software, we confirmed that the CNT films are highly uniform with coefficients of variance (CV) < 10% on 4-inch Si wafers and ∼ 13.8% on G2.5 backplane glasses. High-performance CNT-TFTs with a mobility of 45–55 cm2·V−1·s−1 were obtained using the fabricated CNT films with a high-performance uniformity (CV ≈ 11%–13%) on a 4-inch wafer. To our knowledge, this is the first fabrication and detailed characterization of such large-area, high-purity, semiconducting CNT films for TFT applications, which is a significant step toward manufacturing CNT-TFTs.

Flexible CMOS integrated circuits based on carbon nanotubes with sub-10 ns stage delays

High-performance logic circuits that are constructed on flexible or unconventional substrates are required for emerging applications such as real-time analytics. Carbon nanotube thin-film transistors (TFTs) are attractive for these applications because of their high mobility and low cost. However, flexible nanotube TFTs usually suffer from much lower performance than those built on rigid substrates, and the resulting flexible integrated circuits typically exhibit low-speed operation with logic gate delays of over 1 μs, which severely limits their practical application. Here we show that high-performance carbon nanotube TFTs and complementary circuits can be fabricated on flexible polyimide substrates using a high-yield, scalable process. Our flexible TFTs exhibit state-of-the-art performance with very high current densities (>17 μA μm−1), large current on/off ratios (>106), small subthreshold slopes (<200 mV dec−1), high field-effect mobilities (~50 cm2 V−1 s−1) and excellent flexibility. We also develop a reliable n-type doping process, which allows us to fabricate complementary logic gates and integrated circuits on flexible substrates. With our approach, we build flexible ring oscillators that have a stage delay of only 5.7 ns. High-performance carbon nanotube thin-film transistors and complementary circuits can be fabricated on flexible substrates, including ring oscillators that have a stage delay of only 5.7 ns.

Top-Contact Self-Aligned Printing for High-Performance Carbon Nanotube Thin-Film Transistors with Sub-Micron Channel Length.

Semiconducting single-wall carbon nanotubes are ideal semiconductors for printed thin-film transistors due to their excellent electrical performance and intrinsic printability with solution-based deposition. However, limited by resolution and registration accuracy of current printing techniques, previously reported fully printed nanotube transistors had rather long channel lengths (>20 μm) and consequently low current-drive capabilities (<0.2 μA/μm). Here we report fully inkjet printed nanotube transistors with dramatically enhanced on-state current density of ∼4.5 μA/μm by downscaling the devices to a sub-micron channel length with top-contact self-aligned printing and employing high-capacitance ion gel as the gate dielectric. Also, the printed transistors exhibited a high on/off ratio of ∼105, low-voltage operation, and good mobility of ∼15.03 cm2 V-1s-1. These advantageous features of our printed transistors are very promising for future high-definition printed displays and sensing systems, low-power consumer electronics, and large-scale integration of printed electronics.

Solution-Processed Nanoscale Carbon Nanotube Thin-Film Transistors Fabricated By Electromigration

Solution-processed carbon nanotube thin-film transistors (CNT-TFTs) have been of great scientific and technological attention due to the merits of fabrication processes and structual integration. Significant improvements in material design and process optimization have resulted in high performance CNT-TFTs which are comparable to or better than conventional ones. However, it is still difficult to realize sub-nano-scaled solution-processed CNT-TFTs suitable for integrated circuits and systems. In order to fabricate a sub-nm gap between source and drain electrodes in the channel region of the solution-processed CNT-TFTs, the DC breakjunction method by applying the electric field to trap Au nanoparticles and to form a short bridge was investigated through electromigration. A gradually ramping electric bias was imposed on the contact junctions, thereby breaking the bridge into a sub-nm gap in TFTs. The combination of surface treatment and vacuum thermal annealing increased the density of the nanotubes in the channel region and improved charge injection between the channel and the source electrode. In this presentation, we will demonstrate the process optimization to realize high-performance solution-processed CNT-TFTs with a channel length of ~20 nm and discuss the effect of surface treatment and vacuum thermal annealing on device performance.

High-performance carbon nanotube thin-film transistors on flexible paper substrates

Single-walled carbon nanotubes (SWCNTs) are promising materials as active channels for flexible transistors owing to their excellent electrical and mechanical properties. However, flexible SWCNT transistors have never been realized on paper substrates, which are widely used, inexpensive, and recyclable. In this study, we fabricated SWCNT thin-film transistors on photo paper substrates. The devices exhibited a high on/off current ratio of more than 106 and a field-effect mobility of approximately 3 cm2/V·s. The proof-of-concept demonstration indicates that SWCNT transistors on flexible paper substrates could be applied as low-cost and recyclable flexible electronics.