High-performance Carbon Nanotube Field Research Articles

Performance Evaluation of CNTFETs Fabricated with Carbon Nanotubes of Different Synthesis Methods

Single walled carbon nanotubes (SWCNTs) exhibit extraordinary electronic properties that render it as an exciting candidate to be applied as the active channel of high-performance carbon nanotube field effect transistors (CNTFETs). The electronic properties of SWCNTs have been demonstrated to be dependent on the tube intrinsic properties that includes structural defects, chirality and diameter. Structural tube defects can be affected by the synthesis method and therefore the latter should also affect the device performance. Hence, this paper aims to present the influence of SWCNTs source synthesis method towards the resulting CNTFET device characteristics. A total of four SWCNT samples were sourced from different synthesis methods in fabricating CNTFETs. The synthesis methods are arc-discharge and three different variation of chemical vapor deposition (CVD) processes, which are DIPS, HiPco and CoMoCAT, respectively. Prior to fabrication, the SWCNT samples were characterized via Raman spectroscopy to quantifythe tube defect levels of each sample, which are directly proportional to the G-peak to D-peak height ratio, G/D. Electrical characterization was carried out via 3-terminal field effect I-Vmeasurement to evaluate key device performance parameters such ason-off current ratio, ION/IOFF, transconductance, gm,subthreshold slope, Spand field effect mobility, μFE.Analysis shows that G/Daffects the IOFFmore significantly relative to ION, resulting in increasing ION/IOFF, and hence switching performance, when G/Dincreases. It is shown an increase of ~50% to the G/Dof the SWCNT source resulted in ~ 860% increase in μFE. Based on the correlation between the optical analysis and electrical measurement, weconclude that theSWCNT growth method cansignificantly affectthe CNTFET device performance.

Improved Device Performance in CNTFET Using Genetic Algorithm

The use of carbon nano tubes has been increased in the last decades. This paper presents and evaluates a new method to achieve high-performance Carbon Nano Tube Field Effect Transistor (CNTFET) architecture. The proposed method utilizes genetic algorithm. Using Matlab and genetic algorithm, the best length and radios of CNTFET tubes are given. Our simulation results show that the proposed method provides an improvement in comparison with other methods in terms of performance.

High-performance Carbon Nanotube Field Effect Transistors with High k Dielectric Gate Material

According to Moore's law the dimensions of individual devices in an integrated circuit have been decreased by a factor of approximately two every two years. This scaling down of devices has been the driving force in technological advances since late 20th century. However, as noted by ITRS 2009 edition, further scaling down has faced serious limits related to fabrication technology and device performances as the critical dimension shrunk down to sub-22 nm range. The limits involve electron tunneling through short channels and thin insulator films, the associated leakage currents, passive power dissipation, short channel effects, and variations in device structure and doping. These limits can be overcome to some extent and facilitate further scaling down of device dimensions by modifying the channel material in the traditional bulk MOSFET structure with a single carbon nanotube or an array of carbon nanotubes. Carbon nanotubes field effect transistors (CNTFETs) are one of the most promising candidates for future nanoelectronics. In this paper, the review of CNTFETs is presented. The structure, operation and the characteristics of carbon nanotubes Field effect transistors have been discussed. In future, we expect the performance of CNTFETs will be better by improving CNT quality and on optimizing device structures.

Improving non-suspended carbon nanotube FET performance by using an alumina protective layer

Fabrication of high-performance carbon nanotube field effect transistors (CNFETs) is an essential prerequisite for obtaining competitive CNFET-based gas sensors. In reality, the CNFET performance is heavily affected by lithography-induced resist residues on or around the nanotubes. These impurities aggravate the gate hysteresis and cause high electrical on-resistance of CNFETs. To address this problem, we present an approach using the atomic-layer-deposited alumina as a protective layer to prevent direct contact between carbon nanotubes (CNTs) and patterning resists. The alumina layer can be easily and completely removed from the CNTs prior to contact metallization. Based on the comparison of 491 devices, we find that the median on-resistance is reduced from 247kΩ to 134kΩ by using the alumina protective layer. Additionally, the median hysteresis width extracted from the CNFET transfer characteristics is narrowed dramatically from 2.2V to ∼0.5V. The simplicity of the presented process sequence allows for its easy integration into various fabrication processes involving CNTs.

Design and analysis of a high-performance CNFET-based Full Adder

This article presents a high-speed and high-performance Carbon Nanotube Field Effect Transistor (CNFET) based Full Adder cell for low-voltage applications. The proposed Full Adder cell is composed of two separate modules with identical hardware configurations which generate the Sum and C out signals in a parallel manner. The great advantage of the proposed structure is its very short critical path which is composed of only two carbon nanotube pass-transistors. This design also takes advantage of the unique properties of metal oxide semiconductor field effect transistor-like CNFETs such as the feasibility of adjusting the threshold voltage of a CNFET by adjusting the diameter of its nanotubes to correct the voltage levels as well as to achieve a high performance. Comprehensive experiments are performed in various situations to evaluate the performance of the proposed design. Simulations are carried out using Synopsys HSPICE with 32-nm Complementary Metal Oxide Semiconductor (CMOS) and 32-nm CNFET technologies. The simulation results demonstrate the superiority of the proposed design in terms of speed, power consumption, power delay product, and less susceptibility to process variations, compared to other classical and modern CMOS and CNFET-based Full Adder cells.

Fabrication of Carbon Nanotubes Field Emission Cathode by Composite Plating

Carbon nanotubes (CNTs) have high aspect ratio and have great potential to be applied as the field emission cathode because of its large field enhancement factor. In this work, a high performance carbon nanotube field emission cathode (CNTFC) was fabricated by using a composite plating method. The CNTs were purified by acid solutions and then dispersed in electrobath with nickel ions at temperatures of 60, 70, or 80 degrees C for the electroless plating process on glass substrate. The resulting CNT-Ni composite film has strong adhesion on the glass substrate. The degree of graphitization and the microstructure of the CNTFCs were studied by Raman spectroscopy and scanning electron microscopy. The field emission properties of the CNTFCs show a low turn-on electric field E(on) of about 1.2 V/microm, and a low threshold electric field E(th) of about 1.9 V/microm. Such a composite plating method could be applied to the fabrication of large area CNT field-emission displays.

A process for high yield and high performance carbon nanotube field effect transistors

Carbon nanotube field effect transistors (CNTFETs) have been considered as one of the potential candidates for nanoelectronics beyond Si CMOS. However, it is not easy to have high performance CNTFETs with high yield currently. In this work, we proposed a local bottom-gate (LBG) CNTFETs combined with a novel device concept and optimized process technologies. High performance of CNTFET with low subthreshold swing of 139 mV/dec, high transconductance of 1.27 μS, and high I on/ I off ratio of 10 6 can be easily obtained with Ti source/drain contact after a post annealing process. Record high yield of 74% has been demonstrated. On the basis of the proposed process, lots of high performance CNTFETs can be obtained easily for advanced study on the electrical characteristics of CNTFETs in the future.

High-Performance Carbon Nanotube Field Effect Transistors with a Thin Gate Dielectric Based on a Self-Assembled Monolayer

Individual single-walled carbon nanotube (SWCNT) field effect transistors (FETs) with a 2 nm thick silane-based organic self-assembled monolayer (SAM) gate dielectric have been manufactured. The FETs exhibit a unique combination of excellent device performance parameters. In particular, they operate with a gate-source voltage of only -1 V and exhibit good saturation, large transconductance, and small hysteresis (<or=100 mV), as well as a very low subthreshold swing (60 mV/dec) under ambient conditions. The SAM-based gate dielectric opens the possibility of fabricating transistors operating at low voltages and constitutes a major step toward nanotube-based flexible electronics.

A simple method to fabricate high-performance carbon nanotube field emitters

A simple new method to fabricate carbon nanotube field emitters was developed. Single wall carbon nanotubes with high graphitization were attached on Sn or Ni layered glass substrate in-situ in arc-discharge chamber. Post heat treatments below the deformation temperature of soda-lime glass guaranteed a good mechanical adhesion and electrical contact of the nanotubes. The morphology of the metal electrode layers was examined with the heat treatment temperatures to optimize the heat treatments. The emitters formed on Sn layers showed lower turn-on voltage and higher current density than those formed on Ni layers. A good field emission performance was realized in an emitter where nanotubes were deposited on Sn layer of the thickness 100 nm and annealed at 300∘C. The current density was 2.5 mA/cm2 at 3.5 V/μm. The emitter structure was maintained stable for 8 h.

Fabrication of high performance carbon nanotube field emitters

We report a new fabrication process for high performance carbon nanotube field emitters. The key process of the fabrication method is trim-and-leveling the carbon nanotubes (CNTs) grown in trench structures by employing a polishing process, which leads to a uniform distance from the carbon nanotube tip to the electrode. In order to enable this processing, spin-on-glass liquid is applied over the CNTs to ensure strong adhesion to each other and to the substrate. The emitters thus fabricated revealed extremely stable current–voltage and aging characteristics. A sharp turn-on voltage of ∼1.7 V at 10 μA/cm 2 was also observed. These high performances of the emitters are realized by the uniform distance between leveled emitter tips and the electrode and by the open tube tips achieved through the planarization process using spin-on-glass.

Carbon nanotube transistors and logic circuits

We discuss our recent efforts to develop high performance carbon nanotube field effect transistors (CNTFETs) and logic circuits. By improving the metal nanotube contacts the characteristics of the CNTFETs are greatly enhanced. Analysis shows that the performance of p-type CNTFETs is already competitive to that of silicon p-MOSFETs. In addition to the p-CNTFETs, we present techniques by which ambipolar and pure n-type CNTFETs can be fabricated. A particulary simple process involving the annealing in vacuum of a p-CNTFET is shown to convert it to an n-CNTFET. This conversion is reversible, and re-exposure to oxygen leads to a p-CNTFET. Evidence is found that the key effect of oxygen involves modification of the contact barriers. Having complementary CNTFETs (i.e. p- and n-type) allows us to build the first integrated circuits. We present results on a NOT logic gate. Both an inter-molecular gate involving two separate CNTFETs, and an intra-molecular gate where the logic function is encoded along the length of a single tube are demonstrated.