High-performance Bipolar Technology Research Articles

Device design issues for a high-performance technology with Si or SiGe epitaxial base

Design issues for a high-performance bipolar technology with Si or SiGe epitaxial base are discussed. Narrow and shallow polysilicon emitter formation and extrinsic base design for low base resistance are investigated using selective epitaxy emitter window (SEEW) transistors. In spite of a close proximity of the extrinsic base diffusion to the intrinsic device a cut-off frequency (f T ) up to 50 GHz has been achieved for an emitter width of 0.35 ?m. The depth of the extrinsic base diffusion did affect the collector-base capacitance and indicated that the extrinsic base should be designed in a manner consistent with the circuit operating current density. Further, we discuss in detail the emitter window tolerance for SEEW formation.

High-performance bipolar technology for improved ECL power delay

A new shallow trench process for isolation of bipolar devices is shown to allow butting of the emitter-base junction to the field oxide edge, thereby greatly reducing the overall device size and parasitic capacitances. Emitter-coupled logic (ECL) ring-oscillator measurements demonstrate a significant performance leverage, where a delay of 75 ps is obtained at a power of 1.5 mW per gate (power-delay product of 112 fJ ), an improvement of 17% from the nonbutted case. More conventional nonbutted devices have been fabricated with dopant profiles tailored to reduce intrinsic and extrinsic capacitances. These high-performance designs achieve ECL gate delays as small as 26 ps at 5.3 mW, comparable to the fastest ECL delays reported to date.

A submicrometer high-performance bipolar technology

The description of a submicrometer self-aligned bipolar technology developed to minimize the device topography and to provide shallow profiles for high-performance (ECL) emitter-coupled logic applications is presented. The technology features 0.8- mu m design rules, planar beakless field oxide, polysilicon-filled deep trench isolation, and the use of rapid thermal annealing (RTA). Conventional ECL circuits with 35-ps gate delays, a novel AC-coupled active-pull-down (API) ECL circuit with 21-ps gate delay, and a 1/128 static frequency divider operated at a maximum clocking frequency of 12.5 GHz are demonstrated. >

Isoplanar integrated injection logic: a high-performance bipolar technology

A newly developed technology is discussed. The emphasis of this approach is on achieving high packing density and high performance by use of various process innovations combined with topological design variations. Factors affecting packing density, DC as well as power delay product in I/SUP 2/L are analyzed and design considerations for the new structure are given. The results of computer simulations and measured device parameters and power delay are given. The following gate performance has been obtained at 100-/spl mu/A injector current, /spl beta/u/spl sime/2-4 for all four collectors, speed <10 ns for fan-out of four, speed <5 ns for a fan-out of one. At low currents a speed power product is 0.15 pJ. A packing density of more than 300 gates/mm/SUP 2/ including interconnect and power bussing has been achieved.