High Performance Arithmetic Circuits Research Articles

Analysis of CMOS Logic and Transmission Gate for 64 Bit Parallel Prefix Adders

<span>Parallel prefix adder network is a type of carry look ahead adder structure. It is widely considered as the fastest adder and used for high performance arithmetic circuits in the digital signal processors. In this article, an introduction to the design of 64 bit parallel prefix adder using transmission technique which acquires least no of nodes<strong> </strong>with the lowest transistor<strong> </strong>count and low power consumption is presented. The 64 bit parallel prefix adder is designed and comparison is made between other previously parallel prefix adders. The result shows that the proposed 64 bit parallel prefix adder is slightly better than existing parallel prefix adders and it considerably increases the computation speed.The spice tool is used for analysis with different supply voltages.</span>

Stateful-NOR based reconfigurable architecture for logic implementation

Most commercial Field Programmable Gate Arrays (FPGAs) have limitations in terms of density, speed, configuration overhead and power consumption mostly due to the use of SRAM cells in Look-Up Tables (LUTs), configuration memory and programmable interconnects. Also, hardwired Application Specific Integrated Circuit (ASIC) blocks designed for high performance arithmetic circuits in FPGA reduce the area available for reconfiguration. In this paper, we propose a novel generalized hybrid CMOS-memristor based architecture using stateful-NOR gates as basic building blocks for implementation of logic functions. These logic functions are implemented on memristor nanocrossbar layers, while the CMOS layer is used for selection and connection of memristors. The proposed pipelined architecture combines the features of ASIC, FPGA and microprocessor based designs. It has high density due to the use of nanocrossbar layer and high throughput especially for arithmetic circuits. The proposed architecture for three input one output logic block is compared with conventional LUT based Configurable Logic Block (CLB) having the same number of inputs and outputs; which shows 1.82×area saving, 1.57×speedup and 3.63×less power consumption. The automation algorithm to implement any logic function using proposed architecture is also presented.

Dynamic Current Mode Logic Realization of Digital Arithmetic Circuits

In this paper, we realize a high performance arithmetic circuits which is faster and have lower power consumption using a new dynamic logic family of CMOS and to analyze its performance for arithmetic circuits. This new dynamic logic family is known as Dynamic Current Mode Logic (DyCML). DyCML circuits combine the advantages of MOS current mode logic (MCML) circuits with those of dynamic logic families to achieve high performance at a low-supply voltage with low-power dissipation. A major advantage of the DyCML is the dynamic current source, which achieves smaller delays compared to the basic MCML circuits. Other advantages inherited from MCML are high performance and robustness to supply voltage scaling. DyCML gates reduce power dissipation by reducing the output voltage swing. We compare a set of arithmetic circuits implemented in Dynamic Current Mode Logic with the other dynamic logic styles. Simulation and test results show that DyCML circuits are superior to DDCVS logic styles in terms of power dissipation. A 2-bit multiplier, full adder & xor/xnor gate in DyCML style is fabricated in 180nm CMOS technology. 2-bit multiplier and a full adder dissipate 145.1 µW and 55.14 µW respectively at 40 MHz for a voltage swing of 1.2V in DyCML style.

Performance Analysis of High Speed Domino CMOS Logic Circuits

the demand of low power high performance arithmetic circuits multiplies, during this paper, we aim to introduce a style of latest MT-CMOS domino logic and FTL dynamic logic technique to style adder circuit. The MT-MOS transistors cut back the facility dissipation by minimizing sub threshold run current in the introduced domino logic circuits. The MT-NMOS semiconductor connected in discharging path of output electrical converter may be applied for pipeline structure to scale back the facility consumptions and increase fan-out. Dynamic logic vogue CMOS circuit is employed to enhance the speed and cut back the world of style by decreasing the device count. The introduced FTL dynamic logic circuit improves the performance by evaluating the computational blocks partially before its input signals are formalized and then rapidly perform a final evaluation as soon as the inputs arrive. This dynamic logic formation is like minded for an arithmetic circuit wherever the important path s created of an outsized cascade of inverting gates is created. The mixture of MT-CMOS and dynamic logic circuit provides high fan-out, high change frequencies with each lower delay and dynamic power consumption. The simulation results of those projected low power high performance circuits provide 75% power reduction, three times redoubled high speed operation and active space reduction, whereas revealing lower sensitivity to power provide, temperature, electrical phenomenon load and method variations than the dynamic domino CMOS technologies.

FPGA-based architecture for real time segmentation and denoising of HD video

The identification of moving objects is a basic step in computer vision. The identification begins with the segmentation and is followed by a denoising phase. This paper proposes the FPGA hardware implementation of segmentation and denoising unit. The segmentation is conducted using the Gaussian mixture model (GMM), a probabilistic method for the segmentation of the background. The denoising is conducted implementing the morphological operators of erosion, dilation, opening and closing. The proposed circuit is optimized to perform real time processing of HD video sequences (1,920 × 1,080 @ 20 fps) when implemented on FPGA devices. The circuit uses an optimized fixed width representation of the data and implements high performance arithmetic circuits. The circuit is implemented on Xilinx and Altera FPGA. Implemented on xc5vlx50 Virtex5 FPGA, it can process 24 fps of an HD video using 1,179 Slice LUTs and 291 Slice Registers; the dynamic power dissipation is 0.46 mW/MHz. Implemented on EP2S15F484C3 StratixII, it provides a maximum working frequency of 44.03 MHz employing 5038 Logic Elements and 7,957 flip flop with a dynamic power dissipation of 4.03 mW/MHz.

A current-mode multi-valued adder circuit for multi-operand addition

Static CMOS logic circuits have a robust working performance. However, they generate excessive noise when the switching activity is high. Source-coupled logic (SCL) circuits can be an alternative for analogue-friendly design where constant current is driven from the power supply, independent of the switching activity of the circuit. In this work, a compact current-mode multi-operand adder cell, similar to SCL circuits, is designed. The circuit adds up seven input operands using a technique similar to the (7, 3) counter circuit, but with less active elements when compared to a conventional binary (7, 3) counter. The design has comparable power and delay characteristics compared to conventional SCL implementation. The proposed circuit requires only 69 transistors, where 96 transistors are required for the equivalent SCL implementation. Hence the circuit saves on both transistor count and interconnections. The design is optimised for low power operation of high performance arithmetic circuits. The proposed multi-operand adder circuit is designed in UMC 0.18 µm technology. As an example of application, an 8 × 8 bit multiplier circuit is designed and simulated using HSPICE.

High Speed Multiple Valued Logic Full Adder Using Carbon Nano Field Effect Transistor

High speed Full-Adder (FA) module is a critical element in designing high performance arithmetic circuits. In this paper, we propose a new high speed multiple-valued logic FA module. The proposed FA is constructed by 14 transistors and 3 capacitors, using carbon nano-tube field effect transistor (CNFET) technology. Furthermore, our proposed technique has been examined in different voltages (i.e., 0.65v and 0.9v). The observed results reveal power consumption and power delay product (PDP) improvements compared to existing FA counterparts

A novel low-power full-adder cell with new technique in designing logical gates based on static CMOS inverter

A new low-power full-adder based on CMOS inverter is presented. This full-adder is comprised of inverters. Universal gates such as NOR, NAND and MAJORITY-NOT gates are implemented with a set of inverters and non-conventional implementation of them. In the proposed design approach the time consuming XOR gates are eliminated. As full-adders are frequently employed in a tree-structured configuration for high-performance arithmetic circuits, a cascaded simulation structure is employed to evaluate the full-adders in a realistic application environment. The circuits being studied were optimized for energy efficiency using 0.18μm and 90nm CMOS process technologies. The proposed full-adder shows full swing logic, balanced outputs and strong output drivability. It is also observed that the presented design can be utilized in many cases especially whenever the lowest possible power consumption is targeted. Circuits layout implementations and checking their functionality have been done using Cadence IC package and Synopsys HSpice, respectively.

Low Power and High Performance Arithmetic Circuits in Feedthrough CMOS Logic Family for Low Power Applications

Low Power and High Performance Arithmetic Circuits in Feedthrough CMOS Logic Family for Low Power Applications

A review of 0.18-/spl mu/m full adder performances for tree structured arithmetic circuits

The general objective of our work is to investigate the area and power-delay performances of low-voltage full adder cells in different CMOS logic styles for the predominating tree structured arithmetic circuits. A new hybrid style full adder circuit is also presented. The sum and carry generation circuits of the proposed full adder are designed with hybrid logic styles. To operate at ultra-low supply voltage, the pass logic circuit that cogenerates the intermediate XOR and XNOR outputs has been improved to overcome the switching delay problem. As full adders are frequently employed in a tree structured configuration for high-performance arithmetic circuits, a cascaded simulation structure is introduced to evaluate the full adders in a realistic application environment. A systematic and elegant procedure to scale the transistor for minimal power-delay product is proposed. The circuits being studied are optimized for energy efficiency at 0.18-/spl mu/m CMOS process technology. With the proposed simulation environment, it is shown that some survival cells in stand alone operation at low voltage may fail when cascaded in a larger circuit, either due to the lack of drivability or unsatisfactory speed of operation. The proposed hybrid full adder exhibits not only the full swing logic and balanced outputs but also strong output drivability. The increase in the transistor count of its complementary CMOS output stage is compensated by its area efficient layout. Therefore, it remains one of the best contenders for designing large tree structured arithmetic circuits with reduced energy consumption while keeping the increase in area to a minimum.

Wave steering to integrate logic and physical syntheses

Wave steering is a unified logic and physical synthesis scheme that algorithmically generates high-throughput circuits with fast turn-around times. Binary decision diagram (BDD)-type structures are altered to satisfy certain electrical constraints, embedded in silicon with pass transistor logic (PTL), and pipelined to very fine granularity using a novel two-phase clocking scheme. This direct PTL mapping of a logic representation provides good electrical estimations to a front-end tool like the logic synthesizer at an early phase of the design cycle. We apply our wave steering technique to high throughput computation-intensive datapath combinational circuits. We achieve an average speedup of 4.2 times compared to standard cell (SC) implementations of high performance arithmetic circuits at the cost of only about 76% average increase in area. The results look extremely encouraging; all the more so, considering that we also achieve an average reduction of 27% in latency and 15% in power compared to SC circuits.

Low-power high-performance arithmetic circuits and architectures

A new class of dynamic differential logic families, swing limited logic (SLL), is proposed for low-power high-performance applications. Two implementations of SLL, short-circuit current logic (SC/sup 2/L) and clock-pulse controlled logic (CPCL), are designed. Low power is achieved by aggressively reducing logic swing. Using a 0.35-/spl mu/m CMOS technology and a nominal supply voltage of 3.3 V, an SC/sup 2/L 8-bit carry ripple adder (CRA) is implemented. It offers an order of magnitude less energy-delay product than several other logic families. Furthermore, two multipliers are constructed to demonstrate how SLL can be used in large circuit applications.

Educational design of high-performance arithmetic circuits on FPGA

In many courses of digital system design, a large amount of time is spent introducing the students to architectural and circuit design. A typical laboratory application is the design of arithmetic digital circuits. In the past, as a hardware platform for educational digital design, programmable logic arrays (PLAs) have been widely used. Today, the field programmable gate arrays (FPGAs), seem to be the most suitable technology for this purpose. In this paper, among the many possible design examples, the Authors have chosen the implementation of the radix-4 SRT algorithm for division. As convenient trade-off between area cost and performance, SRT division implementation is being used in many recent general-purpose processors. The circuit offers a sufficient complexity to give practice to the students and to stimulate useful classroom discussions. Moreover, a system for rapid circuit prototyping and testing has been carried out. The prototyping-board allows the transfer of student designs into an SRAM-based FPGA chip and the performance of functional tests of the circuit. The prototyping system is directly controlled by a personal computer via ISA-bus and it allows students concentrate their attention on elaborating the digital design rather than striving with board assembly and PC-to-board communication.