High-performance Application Specific Integrated Circuit Research Articles

A digital phoswich detector using time-over-threshold for depth of interaction in PET

We present the performance of a digital phoswich positron emission tomography (PET) detector, composed by layers of pixilated scintillator arrays, read out by solid state light detectors and an application specific integrated circuit (ASIC). We investigated the use of integrated charge from the scintillation pulses along with time-over-threshold (ToT) to determine the layer of interaction (DOI) in the scintillator. Simulations were performed to assess the effectiveness of the ToT measurements for separating the scintillator events and identifying cross-layer-crystal-scatter (CLCS) events. These simulations indicate that ToT and charge integration from such a detector provide sufficient information to determine the layer of interaction. To demonstrate this in practice, we used a pair of prototype LYSO/BGO detectors. One detector consisted of a 19 × 19 array of 7 mm long LYSO crystals (1.36 mm pitch) coupled to a 16 × 16 array of 8 mm long BGO crystals (1.63 mm pitch). The other detector was similar except the LYSO crystal pitch was 1.63 mm. These detectors were coupled to an 8 × 8 multi-pixel photon counter mounted on a PETsys TOFPET2 ASIC. This high performance ASIC provided digital readout of the integrated charge and ToT from these detectors. We present a method to separate the events from the two scintillator layers using the ToT, and also investigate the performance of this detector. All the crystals within the proposed detector were clearly resolved, and the peak to valley ratio was 11.8 ± 4.0 and 10.1 ± 2.9 for the LYSO and BGO flood images. The measured energy resolution was 9.9% ± 1.3% and 28.5% ± 5.0% respectively for the LYSO and BGO crystals in the phoswich layers. The timing resolution between the LYSO–LYSO, LYSO–BGO and BGO–BGO coincidences was 468 ps, 1.33 ns and 2.14 ns respectively. Results show ToT can be used to identify the crystal layer where events occurred and also identify and reject the majority of CLCS events between layers.

Retiming Pulsed-Latch Circuits With Regulating Pulse Width

A pulsed-latch is an ideal sequencing element for high-performance application-specific integrated circuit designs due to its simple timing model and reduced sequencing overhead. The possibility of time-borrowing while a latch is transparent is deliberately ignored in pulsed-latch circuits to simplify the timing model. However, using more than one pulse width allows another form of time-borrowing, which preserves the simple timing model. The associated problem of allocating pulse widths is called pulse width allocation (PWA); and we combine it with retiming to achieve a shorter clock period in pulsed-latch circuits than can be obtained by retiming or PWA alone, with less requirement for extra latches than standard retiming. An exact solution can be obtained by an integer linear programming, but this is restricted to small circuits. We therefore introduce a practical heuristic, which performs clock skew scheduling to find the minimum clock period and then brings the clock skew as nearly back to zero as possible by converting it to combined retiming and PWA. Experiments with 45 nm technology circuits suggest that the heuristic algorithm achieves a clock period that is close to minimum in most circuits, with an average 23% reduction compared to initial circuit, at an average cost of a 16% increase in the number of latches. On the same benchmarks, standard retiming achieves a 20% reduction in clock period with a 29% increase in the number of latches. The cost in extra area and energy is reasonable.

Design Migration From Peripheral ASIC Design to Area-I/O Flip-Chip Design by Chip I/O Planning and Legalization

Due to higher input/output (I/O) count and power delivery problem in deep submicrometer (DSM) regime, flip-chip technology, especially for area-array architecture, has provided more opportunities for adoption than traditional peripheral bonding design style in high-performance application-specific integrated circuit and microprocessor designs. However, it is hard to tell which technique can provide better design cost edge in usually concerned perspectives. In this paper, we present a methodology to convert a previous peripheral bonding design to an area-I/O flip-chip design. It is based on an I/O buffer modeling and an I/O planning algorithm to legalize I/O buffer blocks with core placement without sacrificing much of the previous optimization in the original core placement. The experimental results have shown that we have achieved better area and I/O wirelength in area-IO flip-chip configuration (especially for pad-limit designs), compared with peripheral bonding configuration in packaging consideration.

An integrated high performance FASTBUS slave interface

A high-performance CMOS FASTBUS slave interface ASIC (application specific integrated circuit) supporting all addressing and data transfer modes defined in the IEEE 960-1986 standard is presented. The FASTBUS slave integrated circuit (FASIC) is an interface between the synchronous FASTBUS and a clock synchronous processor/memory bus. It can work stand-alone or together with a 32-b microprocessor. The FASIC is a programmable device, which makes possible its direct use in many different applications. A set of programmable address mapping windows can map FASTBUS addresses to convenient memory addresses and, at the same time, act as address decoding logic. Data rates of 100 Mbyte/s to FASTBUS can be obtained using an internal first-in first-out (FIFO) in the FASIC to buffer data between the two buses during block transfers. Message passing from FASTBUS, to a microprocessor on the slave module is supported. A compact (70-mm*170-mm) FASTBUS slave piggyback subcard interface, including level conversion between emitter-coupled logic (ECL) and transistor-transistor logic (TTL) signal levels, is implemented using surface mount components and the 208-pin FASIC chip. >