High-order Curvature Compensation Research Articles

CMOS Based Voltage Reference Designs for Sub - 1V

This review paper presents an analysis of the most recent advancements in sub-1V voltage references, addressing the growing demand for ultra-low power consumption and high precision in modern integrated circuits (ICs). Voltage references are critical components in numerous applications, including IoT devices, wearable electronics, and energy-harvesting systems, where power efficiency and accuracy are paramount. It briefly discusses the challenges associated with designing voltage references at such low voltages, such as limited headroom, reduced noise margin, and process variations. Topics include high-order curvature compensation, modified differential pair configurations, and energy-efficient solutions for integrated energy harvesting. These advancements enhance precision and reliability in low-voltage circuits, paving the way for sustainable, low-power electronics and compact devices in the modern digital landscape. It emphasizes the importance of benchmarking different designs against criteria such as power consumption, line regulation, temperature stability, and supply voltage rejection ratio (PSRR). The paper include insights into the state-of-the-art sub-1V voltage reference designs, identification of design trade-offs, and recommendations for future research directions. It underscores the importance of continuous innovation in voltage reference design to address the evolving requirements of ultra-low power electronics. The study here is setting the stage for a detailed analysis of the latest developments in sub-1V voltage references.

A high-accuracy voltage reference with high-order curvature compensation and base-current-canceling techniques

This paper presents a low dropout bandgap voltage reference circuit that combines high output voltage accuracy and low temperature-coefficient in a wide temperature range. The low temperature-coefficient is achieved by an advanced high-order curvature compensation technique, which is implemented by a novel exponential piecewise compensation term in a high-temperature range. A supply noise self-regulation technique is proposed to realize an excellent power supply rejection ratio (PSRR) without using any amplifiers in this paper. The proposed high-accuracy voltage reference is designed in a 2[Formula: see text][Formula: see text]m bipolar process. The circuit generates a reference voltage of 3.3[Formula: see text]V and can operate under a minimum supply voltage of 3.8[Formula: see text]V, while consuming 44.8[Formula: see text][Formula: see text]A. The output voltage accuracy is ± 0.15%. The PSRR at 10[Formula: see text]Hz and 1[Formula: see text]MHz is [Formula: see text][Formula: see text]dB and [Formula: see text][Formula: see text]dB, respectively. The line regulation is 2.45[Formula: see text]ppm/V in a supply voltage range from 3.8[Formula: see text]V to 20[Formula: see text]V. The average temperature coefficient is 11.9[Formula: see text]ppm/∘C in a temperature range from [Formula: see text]C to +125∘C.

A 2.5 V, 2.56 ppm/°C Curvature-Compensated Bandgap Reference for High-Precision Monitoring Applications.

This work presents a high-precision high-order curvature-compensated bandgap voltage reference (BGR) for battery monitoring applications. The collector currents of bipolar junction transistor (BJT) pairs with different ratios and temperature characteristics can cause greater nonlinearities in ΔVEB. The proposed circuit additionally introduces high-order curvature compensation in the generation of ΔVEB, such that it presents high-order temperature effects complementary to VEB. Fabricated using a 0.18 µm BCD process, the proposed BGR generates a 2.5 V reference voltage with a minimum temperature coefficient of 2.65 ppm/°C in the range of −40 to 125 °C. The minimum line sensitivity is 0.023%/V when supply voltage varies from 4.5 to 5.5 V. The BGR circuit area is 382 × 270 μm2, and the BMIC area is 2.8 × 2.8 mm2.

A curvature-compensated bandgap voltage reference with a temperature coefficient trimming circuit

This paper presents an advanced topology of bandgap voltage reference (BGR) which consists of a novel curvature-compensated circuit and a current-mode trimming circuit. A positive-temperature-coefficient (positive-TC) nonlinear term is produced in the difference between the base-emitter voltages of two bipolar junction transistors (ΔVBE) to realize the high-order curvature compensation. The ΔVBE is generated by adding a negative-TC current into the bandgap core. Owing to the compensated ΔVBE, the BGR could be fine-tuned by an innovative current-mode trimming circuit which takes less area and achieves a larger trimming range. Benefiting from the trimming circuit, the PVT stabilities of proposed BGR are improved. Designed in a 0.18 μm HVCMOS process, the BGR occupies an active area of 267μm×226μm. The post-layout simulation results show the BGR reaches a low TC of 1.64 ppm/∘C in a wide range of -55 °C to 125 °C.

A 2.5 ppm/°C Voltage Reference Combining Traditional BGR and ZTC MOSFET High-Order Curvature Compensation

This brief presents a voltage reference with high-order curvature compensation based on the zero temperature coefficient (ZTC) of MOSFET. The proposed voltage reference uses a conventional current reference to generate a constant current as of the bias of ZTCMOS. A curvature compensation method based on the α power model is combined with the conventional curvature compensation method to obtain a low temperature coefficient. Test results of the proposed voltage reference fabricated with the CSMC 0.18 μm CMOS process demonstrate that the output voltage is 628 mV. The trimmed temperature coefficient achieves 2.5 ppm/°C. The line sensitivity is 0.03 %/V, the chip area is 0.024 mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> , power consumption is 77 μW. The simulated power supply rejection ratio (PSRR) reaches -91.4 dB at 100 MHz.

A 1.2 V, 3.0 ppm/°C, 3.6 μA CMOS bandgap reference with novel 3-order curvature compensation

This paper presents a bandgap reference with a high-order curvature compensation circuit which can improve the temperature coefficient (TC) in a wide temperature range. The proposed compensation circuit includes a second-order and a third-order curvature current generators as well as an I-V converter. These two curvature currents are achieved by utilizing the exponential behavior of sub-threshold MOSFET and used for compensating the high-order temperature dependence of BJT base-emitter voltage via I-V converter. The proposed BGR is implemented in a CMOS 0.18 μm process with the active area of 0.056 mm2. Measurements on ten samples showed that at the minimum supply voltage 1.2 V, the TC varies from 1.7 to 6.9 ppm/°C over a temperature range of 170 °C (−45 °C–125 °C) with an average value of 3.0 ppm/°C and the total current consumption of 3.6 μA at room temperature. In the supply voltage range of 1.2–1.8 V, the line regulation (LR) is 0.025%/V.

Negative voltage bandgap reference with multilevel curvature compensation technique**Project supported by the Fund of Liaoning Province Education Department (No. L2013045).

A novel high-order curvature compensation negative voltage bandgap reference (NBGR) based on a novel multilevel compensation technique is introduced. Employing an exponential curvature compensation (ECC) term with many high order terms in itself, in a lower temperature range (TR) and a multilevel curvature compensation (MLCC) term in a higher TR, a flattened and better effect of curvature compensation over the TR of 165 °C (−40 to 125 °C) is realised. The MLCC circuit adds two convex curves by using two sub-threshold operated NMOS. The proposed NBGR implemented in the Central Semiconductor Manufacturing Corporation (CSMC) 0.5 μm BCD technology demonstrates an accurate voltage of −1.183 V with a temperature coefficient (TC) as low as 2.45 ppm/°C over the TR of 165 °C at a −5.0 V power supply; the line regulation is 3 mV/V from a −5 to −2 V supply voltage. The active area of the presented NBGR is 370 × 180 μm2.

A 1.2-V 4.2-&lt;formula formulatype="inline"&gt; &lt;tex Notation="TeX"&gt;$\hbox{ppm}/^{\circ}\hbox{C}$&lt;/tex&gt;&lt;/formula&gt; High-Order Curvature-Compensated CMOS Bandgap Reference

This study presents a high-precision CMOS bandgap reference (BGR) circuit with low supply voltage. The proposed BGR circuit consists of two BGR cores and a curvature correction circuit, which includes a current mirror and a summing circuit. Two BGR cores adopt conventional structures with the curvature-down characteristics. A current-mirror circuit is proposed to implement one of the BGR cores to have the curvature-up characteristic. Selection of the appropriate resistances in the BGR cores results in one reference voltage with a well balanced curvature-down characteristic and another reference voltage with an evenly balanced curvature-up characteristic. The summation of these reference voltages is proposed to achieve a high-order curvature compensation. This curvature correction circuit causes the proposed BGR circuit without any trimming to show a measured temperature coefficient (TC) as low as 4.2 ppm/°C over a wide temperature range of 160 °C (-40 ~ 120 °C) at a power supply voltage of 1.2 V. The average TC for 8 random samples is approximately 9.3 ppm/°C. The measured power-supply rejection ratio (PSRR) of -30 dB is achieved at the frequency of 100 kHz. The total chip size is 0.063 mm 2 with a standard 0.13-μm CMOS process.

A Novel 1.2–V 4.5-ppm/°C Curvature-Compensated CMOS Bandgap Reference

This paper proposes a novel CMOS bandgap reference (BGR) with high-order curvature-compensation by using MOS transistors operating in weak inversion region. The mechanism of the proposed curvature-compensation technique is analyzed thoroughly and the corresponding BGR circuit was implemented in standard CMOS 0.18 μm technology. The experimental results show that the proposed BGR achieves 4.5 ppm/°C over the temperature range of -40°C to 120°C at 1.2 V supply voltage. It consumes only 36 μA. In addition, it achieves line regulation performance of 0.054%/V. It is suitable for low-power applications requiring references with high precision.

A 3.2 ppm/°C curvature-compensated bandgap reference with wide supply voltage range

A novel bandgap reference (BGR) with low temperature and supply sensitivities, which is compatible with standard Bipolar and BiCMOS processes, is presented in this paper. Utilizing exponential curvature compensation (ECC) and translinear loop circuit (TLC), high-order curvature compensation is realized to reduce temperature drift. Besides, two feedback loops are embedded in the circuit to enhance the stability and to reduce the dependence on supply voltage. Experimental results of the proposed BGR implemented with 1-μm Bipolar process demonstrate that a temperature coefficient (TC) of 3.2ppm/°C is realized, a power supply rejection ratio (PSRR) of 60dB is achieved without filtering capacitors, and the line regulation is better than 0.088mV/V from 3.5V to 30V supply voltage dissipating a maximum supply current of 39μA. The active area of the proposed BGR is 700μm×750μm.

A sub-1 V high-precision CMOS bandgap voltage reference

A third-order, sub-1 V bandgap voltage reference design for low-power supply, high-precision applications is presented. This design uses a current-mode compensation technique and temperature-dependent resistor ratio to obtain high-order curvature compensation. The circuit was designed and fabricated by SMIC 0.18 μm CMOS technology. It produces an output reference of 713.6 mV. The temperature coefficient is 3.235 ppm/°C in the temperature range of −40 to 120 °C, with a line regulation of 0.199 mV/V when the supply voltage varies from 0.95 to 3 V. The average current consumption of the whole circuit is 49 μA at the supply voltage of 1 V.

A Curvature-Compensated, High Power Supply Rejection CMOS Bandgap Reference for MEMS Micro-Accelerometer

The reference is an important part in the accelerometer system. With the development of science and technology, the request of the performance of accelerometers is increasingly higher and the precision of reference directly affects the performance of accelerometers. Therefore, a reference voltage applicable to accelerometers is presented based on the analysis of basic principles of conventional bandgap reference (BGR) in this paper. A high-order curvature compensation technique, which uses a temperature dependent resistor ratio generated by a high poly resistor and a nwell resistor, effectively serves to reduce temperature coefficient of proposed reference voltage circuit and to a large extent improve its performance. To achieve a high power supply rejection ratio (PSRR) over a broad frequency range, a pre-regulator is introduced to remain the supply voltage of the core circuit of BGR relatively independent of the global supply voltage. The proposed circuitry is designed in standard 2.0μm CMOS process. The simulated result shows that the average temperature coefficient is less than 2ppm/°C in the temperature range from -40 to 120°C. The improvement on temperature coefficient (TC) is about 10 times reduction compared to the conventional approach. And the PSR at DC frequency and 1kHz achieves -107 and -71dB respectively at 9.0V supply voltage.

A high-order curvature compensation technique for bandgap voltage reference using subthreshold MOSFETs

A bandgap voltage reference with high-order curvature compensation is presented in this study. It exploits subtraction and derivative equalisation of currents generated from two complementary NMOS and PMOS bandgap references (BGRs) using subthreshold MOSFETs. By equating the derivative with respect to temperature of the two currents, generated by the complementary bandgaps, and subtracting these currents, an accurate high-order curvature compensation is achieved. To overcome problems due to the limited input common-mode range of opamps used in BGRs, a transimpedance amplifier with new accurate current compensation that tracks the temperature variation is proposed. This bandgap is implemented using the 0.18 μm CMOS process with a supply voltage as low as 0.7 V. At 0.8 V power supply and an output reference voltage of 386 mV, the proposed circuit achieves a temperature coefficient of 19 ppm/°C from 0 to 130°C. The power consumption is 119 μW and the power supply reduction ratio is 24 dB at 1 kHz.

A 0.52 ppm/°C high-order temperature-compensated voltage reference

This paper proposed a new high-order curvature compensation technique for a new bandgap voltage reference structure using the temperature characteristics of current gain β and emitter bandgap narrowing factor ΔE G of a lateral NPN bipolar transistor. The new structure can produce two voltage references, which are 1.209 and 2.418 V, respectively. The simulation results show that the temperature coefficients of the two output voltage are 0.52 ppm/°C, the PSRR is more than 60 dB for frequencies at 10 kHz, and the circuit dissipates 0.18 mW with 5-V supply.