High Normal Field Research Articles

Mobility degradation under a high effective normal field in an inversion layer of 4H-SiC (0001) metal–oxide–semiconductor structures annealed in POCl3

Mobility degradation under a high effective normal field (1 MV cm−1 < E eff < 2 MV cm−1) in an inversion layer of 4H-silicon carbide (SiC) (0001) metal–oxide–semiconductor field-effect transistors (MOSFETs) annealed in POCl3 is investigated by applying a negative body bias (0 V ≥ V BS ≥ −40 V). The effective channel mobility (μ eff) is proportional to E eff −2.3–−2.2 in the range 1 MV cm−1 ≤ E eff. On the basis of the obtained results, the authors propose that the mobility degradation in the high-E eff region is caused by strong surface roughness scattering in SiC MOSFETs with a very low interface state density.

Effective channel mobility in phosphorus-treated 4H-SiC (0001) metal-oxide-semiconductor field-effect transistors with various p-body doping concentrations

Phosphorus treatment, which can substantially reduce the interface state density (D it), was used to investigate the impact of D it on effective channel mobility (μ eff) of 4H-SiC (0001) metal-oxide-semiconductor field-effect transistors (MOSFETs). A high μ eff of 126 cm2 V−1 s−1, which exceeds the reported phonon-limited mobility of 83 cm2 V−1 s−1 determined from Hall mobility of nitridation-treated MOSFETs, at a high effective normal field of 0.57 MV cm−1 was obtained in MOSFETs fabricated on a high-purity semi-insulating 4H-SiC substrate at room temperature. This high mobility may be caused by the difference of the density of electrons trapped at the interface states.

Simulation Analysis of Electrical-Thermal-Fluid Coupling Property for Supporting Insulation in SF6 Filled HVDC Apparatus

Supporting insulation in SF <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">6</sub> -insulated high voltage direct current (HVDC) apparatus is a complicated issue as it involves the coupling behavior of electric field distribution, heat transfer process, and fluid property of SF <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">6</sub> gas. So far, comprehensive work investigating the insulation performance in this multiphysics coupled field has been absent. In this article, the distribution characteristics of state parameters in SF <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">6</sub> -insulated ±800-kV dc wall bushing have been simulated and analyzed under various coupled fields. The simulation result shows that, when the fluid behavior of SF <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">6</sub> gas is taken into consideration, the temperature and electric field distribution are substantially different from those in previous studies. Particularly, the postinsulator right above the HV conductor suffers from the concentration of high normal electric field, high tangential field, and a relative high temperature near the metal shell side, which greatly threatens the long-term insulation performance of the insulator and increases the risk of flashover. Furthermore, this article has investigated the effect of different supporting structures and material properties on the insulation performance of the bushing, based on which suggestions for insulator layout and material modulation are proposed. This article can serve as a reference for subsequent design and fault analysis on SF <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">6</sub> -insulated HV apparatus.

Carrier transport properties in inversion layer of Si-face 4H–SiC MOSFET with nitrided oxide

We propose a method to evaluate the carrier transport properties in the inversion layer of 4H–SiC metal-oxide-semiconductor field-effect transistors (MOSFETs) experimentally. Our approach differs from conventional methods, which have adjusted the parameters in conventional mobility models. Intrinsic phonon-limited mobility (μphonon) in the SiC MOSFET was observed by suppressing the severe impact of Coulomb scattering on the SiC MOS inversion layer by lowering the acceptor concentration (NA) of the p-type well region to the order of 1014 cm−3. In this study, we investigated the carrier transport properties in the inversion layer of Si-face 4H–SiC MOSFETs with nitrided oxide. It is revealed that the μphonon of the SiC MOSFET is a quarter or less than the conventionally presumed values. Additionally, surface roughness scattering is found not to be the most dominant mobility-limiting factor even at high effective normal field (Eeff) for the SiC MOSFET. These results demonstrate that conventional understanding of carrier scattering in the SiC MOS inversion layer should be modified, especially in the high Eeff region.

Impact of Postdeposition Annealing Ambient on the Mobility of Ge nMOSFETs With 1-nm EOT Al2O3/GeOx/Ge Gate-Stacks

The impact of postdeposition annealing (PDA) ambient on electrical properties of thin equivalent oxide thickness (EOT) Al2O3/GeO x /Ge gate-stacks is investigated. It is found that the surface states inside the conduction band of Ge are significantly suppressed by 40% through PDA with atomic deuterium ambient. As a result, enhancement of the effective mobility in the Ge nMOSFETs is realized in high normal field region. The electron mobility of 396 cm2/Vs is achieved at $N_{s}$ of $10^{13}$ cm $^{-2}$ with small EOT of $\sim 1$ nm, which is similar to the highest mobility reported so far at such small EOT range.

Comparison of Different Scattering Mechanisms in the Ge (111), (110), and (100) Inversion Layers of nMOSFETs With Si nMOSFETs Under High Normal Electric Fields

In this paper, we report, for the first time, that surface roughness scattering is not necessarily the dominant scattering mechanism in the high-normal-field region of Ge nMOSFETs. This statement is quite different from the well-recognized situation in Si MOSFETs. In Ge(100), phonon scattering is dominant in the high-field region. Thus, it is difficult to increase the high-normal-field mobility in Ge(100) nMOSFETs by controlling the interface roughness. In contrast, because Ge(111) and Ge(110) are free of intervalley phonon scattering, the high-field mobility in Ge(111) and Ge(110) nMOSFETs could be enhanced by the Ge interface engineering. Furthermore, different from that in Si nMOSFETs, mobility limited by surface roughness scattering in Ge nMOSFETs shows a strong temperature dependence due to the valley occupancy change of electrons. The results in this paper should facilitate efforts to increase the high-normal-field mobility in Ge nMOSFETs.

Impact of Channel Orientation on Electrical Properties of Ge p- and n-MOSFETs With 1-nm EOT Al2O3/GeOx/Ge Gate-Stacks Fabricated by Plasma Postoxidation

The impact of surface orientations on electrical characteristics of Ge pand n-channel MOSFETs with ultrathin equivalent oxide thickness Al <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> O <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">3</sub> /GeOx/Ge gate-stacks is systematically investigated. It is found that (100), (110), and (111) GeOx/p-Ge metal-oxide-semiconductor (MOS) interfaces have a similar interface trap density (D <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">it</sub> ) level, but (100) GeO <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">x</sub> /n-Ge MOS interfaces exhibit the lowest D <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">it</sub> . As a result, the highest peak mobility is obtained in (110) Ge pMOSFETs for holes and in (100) Ge nMOSFETs for electrons. The higher interface state density is observed inside valence band of Ge for (110) GeO <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">x</sub> /Ge MOS interface and inside conduction band of Ge for (110) and (111) GeO <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">x</sub> /Ge MOS interfaces, leading to the significant effective mobility reduction in high normal field for (110) Ge pMOSFETs, and (110) and (111) Ge nMOSFETs. It is also confirmed that decrease of plasma oxidation temperature is also effective in reduction of the interface roughness at (100) to (111) GeO <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">x</sub> /Ge interfaces, resulting in clear enhancement of both hole and electron mobility in high normal field region.

Physical Origins of High Normal Field Mobility Degradation in Ge p- and n-MOSFETs With GeO x /Ge MOS Interfaces Fabricated by Plasma Postoxidation

Mechanisms of the mobility degradation in high normal field (or Ns) in Ge pand n-metal-oxide-semiconductor field-effect transistors (MOSFETs) with plasma postoxidation GeO <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">x</sub> /Ge MOS interfaces: 1) carrier trapping due to surface states; 2) surface roughness scattering; and 3) electron transfer into the Δ valleys with the high effective mass, have been systematically investigated. It is confirmed that the existence of surface states inside the valence band and the conduction band of Ge results in over estimation of the mobile inversion carrier concentration and the rapid reduction of the effective mobility. It is also found that the Hall hole and electron mobility in high N <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">s</sub> region agree well with the theoretical surface roughness limited mobility, indicating that the high N <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">s</sub> mobility in Ge MOSFETs are still significantly limited by surface roughness scattering. On the other hand, any evidence of the carrier repopulation into the subband with low mobility has not been experimentally identified in both Ge pand n-MOSFETs yet.

AC electro-osmotic mixing induced by non-contact external electrodes

We demonstrate efficient mixing in a micro-fluidic reservoir smaller than 10 microL using ac electro-osmosis driven by field-induced polarization. Our mixing device, of that electrodes are outside of the mixing unit, consists of three circular reservoirs (3mm in diameter) connected by a 1 mm x 1 mm channel. Unlike dc electro-osmosis, whose polarization is from charged substrate functional groups, this new mechanism uses the external field to capacitively charge the surface and the surface capacitance becomes the key factor in the electrokinetic mobility. The charging and mixing are enhanced at tailor-designed channel corners by exploiting the high normal fields at geometric singularities. The induced surface dielectric polarization and the resulting electric counter-ion double layer produce an effective Zeta potential in excess of 1 V, over one order of magnitude larger than the channel Zeta potential. The resulting ac electro-osmotic slip velocity scales quadratically with respect to the applied field, in contrast to the linear scaling of dc electro-osmosis and at 1cm/s and larger, exceeds the classical dc values by two orders of magnitude. The polarization is non-uniform at the corners due to field leakage to the dielectric substrate and the inhomogeneous slip velocity produces intense mixing vortices that effectively homogenize solutes in 30s in a 3mm reservoir, in contrast to hour-long mixing by pure diffusion.

Thermal and electrical analysis of alumina and beryllia coax high-power windows under irradiation

Characteristics of dielectric insulators in vacuum windows of coaxial 10 to 100 MHz transmission lines in high-power steady-state use under irradiation are simulated with respect to electric, nuclear, mechanical, and thermal properties. Neutron fluence /spl sim/5/spl times/10/sup 18/ n/cm/sup 2/ at the window is obtained to be sufficiently small to allow beryllia, but not alumina, to be used as dielectric. In beryllia (10/sup -3/ displacements per atom (dpa) due to irradiation) or in un-irradiated alumina (97.5% purity), the temperature is found to rise by not more than 125/spl deg/C with maximum stress <140 MPa for 50 kV peak voltage at 60 MHz, provided niobium, titanium or materials with similar thermal expansion coefficients are used in water cooled conductors. The tangential electric field is kept well below the surface discharge limit 2 MV/m by using potential rings together with a sufficiently large inclination angle of the conical ceramic with respect to the radial coaxial direction, but high normal fields exceeding the vacuum breakdown limit are obtained near the potential rings. Abandoning the potential rings and deforming the equipotential lines by shaping the ceramic-conductor joint can reduce both tangential and normal field components below the breakdown limit, which appears to be in agreement with recent voltage test experiments.

Correlation between inversion layer mobility and surface roughness measured by AFM

The correlation between inversion layer mobility of MOSFET's and surface micro-roughness of the channel has been studied using split CV measurements and AFM analysis. The mobility at high normal field decreases with increasing the surface roughness over a wide range of roughness from 0.3 nm to 4.3 nm (RMS). The trend is the same even for very thin gate oxides down to 3 nm. Careful AFM measurements are used to show that the gate oxide thickness doesn't affect the surface roughness, supporting the independence of mobility on the gate oxide thickness.

Effect of pressure on the growth of the crystallites of low pressure chemical vapour deposited polycrystalline silicon films and the effective electron mobility under high normal field in thin film transistors

The morphology of the polysilicon films obtained at temperatures below the softening point of glass, by low pressure chemical vapour deposition as related to pressure of the pure silane used for the growth is examined and is related to the characteristics of the thin film transistors from these films in order to establish the optimum conditions of the switching performance in their application as pixel elements in peripherals.

Effect of pressure on the growth of crystallites of low-pressure chemical-vapor-deposited polycrystalline silicon films and the effective electron mobility under high normal field in thin-film transistors

The morphology of polycrystalline films grown by low-pressure chemical-vapor deposition (LPCVD) is investigated by transmission electron microscopy (TEM) as a function of the film thickness, the deposition pressure, and the level of contamination. An orientation filtering mechanism, due to the growth-velocity competition in the early stage of growth, is responsible for the preferred orientation of the films. The size of the crystallites, the surface roughness, and the type of the structural defects are investigated by combined cross-sectional and plane-view TEM analysis. In polycrystalline silicon thin-film transistors (TFTs), the influence of surface roughness scattering on the mobility is investigated by measuring the effective electron mobility under high effective normal field at 295 and 77 K. Although the surface curvature is increased when the deposition pressure is decreased, the surface roughness scattering is constant in the deposition pressure range from 40 to 0.5 mTorr. By decreasing the deposition pressure from 40 to 10 mTorr, although the grain size increases, the TFT performance degrades due to the following factors: (a) the increase of the grain-boundary trap density which is related to the change of the mode of growth at 10 mTorr; and (b) the increase of impurity contamination in the environment of the LPCVD system with constant silane flow rate at all pressures. At a deposition pressure of 0.5 mTorr the TFT performance is improved indicating that the grain size is the prevailing key factor.

Influence of high substrate doping levels on the threshold voltage and the mobility of deep-submicrometer MOSFETs

The high levels of substrate doping needed in deep-submicrometer MOS devices affect device properties strongly. The authors present a detailed experimental study of high-doping effects on the threshold voltage, which is shown to be affected by the quantum-mechanical splitting of the energy levels in the conduction band. A simple expression to account for these effects is proposed and the consequences for device scaling and design are discussed. Furthermore, the increasing levels of substrate doping and high normal electric fields affect the channel mobility through Coulomb and surface-roughness scattering. Several empirical models for the surface mobility are compared with the characteristics of experimental devices. >

Effects of high normal electric fields in deep submicron MOSFET's

The implications of high normal electric fields in MOSFET's on device simulations are discussed. Comparison of simulations with data of experimental MOS devices shows that, even at room temperature, the electric fields generated by high levels of channel doping affect the threshold voltage by quantum-mechanical effects. Furthermore, the surface mobility is reduced by high normal fields, but can still be modeled accurately when calculated as a function of the effective electric field.

Improved reliability characteristics of submicrometer nMOSFETs with oxynitride gate dielectric prepared by rapid thermal oxidation in N/sub 2/O

Submicrometer MOSFETs with ultrathin oxynitride gate dielectric grown in pure N/sub 2/O ambient were studied. The peak mobility of oxynitride is 5% lower than that of control oxide. However, the oxynitride shows 10% less mobility degradation under high normal field. Compared with the control oxide device, the oxynitride device shows significantly less degradation under channel hot-electron stress. The lifetime of the oxynitride device is approximately one order of magnitude longer than that of the control oxide sample. Significant improvement of device reliability is due to the nitrogen incorporation during the oxidation process. >

Study of inversion layer mobility in metal-oxide-semiconductor field-effect transistors with reoxidized nitrided oxides

The carrier effective mobility μeff in the inversion layer for both n- and p-channel metal-oxide-semiconductor field-effect transistors with ultrathin gate dielectrics prepared by rapid thermal reoxidation (RTO) of rapid thermal nitrided (RTN) SiO2 has been studied. It is found that although RTN/RTO degraded the low-field μeff, it improved significantly the electron μeff under high normal field compared to control SiO2. The effect of RTN/RTO on the hole effective mobility has also been examined and found to be quite different than on the electron effective mobility. A physical mechanism is discussed to account for the observation.

Electron Mobility in Si Inversion Layers

Gate voltage dependence of electron mobility in n-channel MOSFETs is investigated using Hall effect and channel conductance measurements at room temperature and at 77 K. The electron mobilities obtained by the two different methods show a good agreement with each other and exhibit a decrease with increasing gate voltage in the region of high effective normal field. The theoretical model for electron mobility is given based on the interactions of two-dimensional electron gas confined in the inversion layer with acoustic phonons, intervalley phonons, surface-roughness and ionized impurities. An analytical expression is obtained for the electron mobility, where three types of f- and g-intervalley phonons are included. The calculated results show a good agreement with the experimental data and the decrease in the mobility at high effective normal field is interpreted in terms of surface-roughness scattering which results in Eeff-2 dependence at high normal fields.

Improved transconductance under high normal field MOSFETs with ultrathin nitrided oxides

The gate-voltage dependence of electron mobility at 298 and 82 K in MOSFETs with nanometer-range thin (reoxidized) nitrided oxides prepared by rapid thermal processing (RTP) at 900-1150 degrees C for 15-300 s is discussed. Rapid nitridation improves the mobility and current derivability under high normal field over thermally grown oxides at both temperatures: the transconductance g/sub m/ at a gate drive of 3.5 V is improved by half an order of magnitude, whereas the peak g/sub m/ remains comparable to that of an oxide. Nitridation also avoids the negative g/sub m/ observed at 82 K for an oxide MOSFET. These improvements are substantially unchanged by additional reoxidations. >

Modeling of transconductance degradation and extraction of threshold voltage in thin oxide MOSFET's

In this paper, we discuss the low-drain voltage transconductance behavior of the MOSFET due to surface mobility variation, interface states and small geometry, and its application in threshold voltage determination. We modify the Pao-Sah drain current model to incorporate a mobility model and obtain 3% accuracy from subthreshold to very strong inversion for a wide range of substrate biases. The effects of non-ideal scaling, finite inversion layer thickness, surface roughness mobility degradation under high normal electric fields and interface states on the transconductance behavior are discussed. We observe the peak transconductance increases with substrate bias in short-channel devices and decreases with substrate bias in long-channel devices. Finally, we show the threshold voltage can be determined from the gate voltage at which the rate of transconductance change ( ∂g m ∂V GS ) is a maximum. This threshold voltage is identifiable with a known band-bending (surface potential) of the substrate (φ s ⋍ 2φ F + V SB ) , from which the band-bending at all gate biases can be calculated. The transconductance change (TC) method is insensitive to device degradations (e.g. mobility, series resistance, hot-carrier) in contrast to the conventional method of linear extrapolation to zero drain current.