High Mobility Ge Research Articles

Lateral Mn5Ge3 spin-valve in contact with a high-mobility Ge two-dimensional hole gas

Abstract Ge two-dimensional hole gases (2DHG) in strained modulation-doped quantum-wells represent a promising material platform for future spintronic applications due to their excellent spin transport properties and the theoretical possibility of efficient spin manipulation. Due to the continuous development of epitaxial growth recipes extreme high hole mobilities and low effective masses can be achieved, promising an efficient spin transport. Furthermore, the Ge 2DHG can be integrated in the well-established industrial complementary metal-oxide-semiconductor (CMOS) devices technology. However, efficient electrical spin injection into a Ge 2DHG—an essential prerequisite for the realization of spintronic devices—has not yet been demonstrated. In this work, we report the fabrication and low-temperature magnetoresistance (MR) measurements of a laterally structured Mn5Ge3/Ge 2DHG/ Mn5Ge3 device. The ferromagnetic Mn5Ge3 contacts are grown directly into the Ge quantum well by means of an interdiffusion process with a spacing of approximately 130 nm, forming a direct electrical contact between the ferromagnetic metal and the Ge 2DHG. Here, we report for the first time a clear MR signal for temperatures below 13 K possibly arising from successful spin injection into the high mobility Ge 2DHG. The results represent a step forward toward the realization of CMOS compatible spintronic devices based on a 2DHG.

High mobility Ge 2DHG based MODFETs for low-temperature applications

Modulation-doped field-effect transistors (MODFET) that are typically based on either a two-dimensional electron gas or a two-dimensional hole gas (2DHG) are highly suitable for low-temperature applications due to the high mobilities attained by the charge carriers in the device channel. The Ge 2DHG is particularly interesting, since Ge exhibits the highest hole mobility among all semiconductors. In this paper, we report on the temperature-dependent direct current-characteristics of normally-on MODFETs based on a high mobility Ge 2DHG. Here, we specifically investigate device characteristics down to cryogenic temperatures and analyze the impact of different MOD-doping on device performance. We find that the largest On-Off ratio of and lowest sub-threshold swing (SS) of at a temperature of are attained for a MOD-doping of , while the highest effective mobility is obtained from a device with a MOD-doping of . Furthermore, while effective mobilities in the devices are strongly reduced compared to Hall mobilities measured in the unstructured Ge 2DHGs, both quantities can be seen to follow a similar trend. Our results motivate further investigations of Ge 2DHG MODFETs for applications in cryogenic low-noise amplifiers, besides their well-established potential for spintronic applications.

Mobility enhancement techniques for Ge and GeSn MOSFETs

The performance enhancement of conventional Si MOSFETs through device scaling is becoming increasingly difficult. The application of high mobility channel materials is one of the most promising solutions to overcome the bottleneck. The Ge and GeSn channels attract a lot of interest as the alternative channel materials, not only because of the high carrier mobility but also the superior compatibility with typical Si CMOS technology. In this paper, the recent progress of high mobility Ge and GeSn MOSFETs has been investigated, providing feasible approaches to improve the performance of Ge and GeSn devices for future CMOS technologies.

High Electron Mobility Germanium FinFET Fabricated by Atomic Layer Defect-Free and Roughness-Free Etching

We investigated a high electron mobility Ge FinFET fabricated by defect-free and roughness-free atomic layer neutral beam etching (NBE) compared with one fabricated by conventional plasma etching (PE). The etching interface roughness and defect were estimated by high-resolution transmission electron microscopy (TEM). In the case of using atomic layer defect-free NBE, the root-mean-square roughness of the Ge Fin sidewall surface is 1/3 times smaller than that using PE. Then, the electron mobility of Ge FinFET was improved by 1.65 times compared with that of a PE etched FinFET sample. For the subthreshold swing, the defect density of the interface between the Ge and gate dielectric film was improved by NBE. Ioff average currents of NBE and PE were around 18.1 and 57.6 nA/μm, respectively. As a result, NBE reduces the off-leakage current to 1/3 times less than PE. This corresponded to the differences in surface roughness and defect generation between NBE and PE. Therefore, we found that NBE could achieve a good performance by defect-free and atomically-flat etching the surface.

High-electron-mobility (370\u2009cm2/Vs) polycrystalline Ge on an insulator formed by As-doped solid-phase crystallization

High-electron-mobility polycrystalline Ge (poly-Ge) thin films are difficult to form because of their poor crystallinity, defect-induced acceptors and low solid solubility of n-type dopants. Here, we found that As doping into amorphous Ge significantly influenced the subsequent solid-phase crystallization. Although excessive As doping degraded the crystallinity of the poly-Ge, the appropriate amount of As (~1020 cm−3) promoted lateral growth and increased the Ge grain size to approximately 20 μm at a growth temperature of 375 °C. Moreover, neutral As atoms in poly-Ge reduced the trap-state density and energy barrier height of the grain boundaries. These properties reduced grain boundary scattering and allowed for an electron mobility of 370 cm2/Vs at an electron concentration of 5 × 1018 cm−3 after post annealing at 500 °C. The electron mobility further exceeds that of any other n-type poly-Ge layers and even that of single-crystal Si wafers with n ≥ 1018 cm−3. The low-temperature synthesis of high-mobility Ge on insulators will provide a pathway for the monolithic integration of high-performance Ge-CMOS onto Si-LSIs and flat-panel displays.

Polycrystalline thin-film transistors fabricated on high-mobility solid-phase-crystallized Ge on glass

Low-temperature formation of Ge thin-film transistors (TFTs) on insulators has been widely investigated to improve the performance of Si large-scale integrated circuits and mobile terminals. Here, we studied the relationship between the electrical properties of polycrystalline Ge and its TFT performance using high-mobility Ge formed on glass using our recently developed solid-phase crystallization technique. The field-effect mobility μFE and on/off currents of the accumulation-mode TFTs directly reflected the Hall hole mobility μHall, hole concentration, and film thickness of Ge. By thinning the 100-nm thick Ge layer with a large grain size (3.7 μm), we achieved a high μHall (190 cm2/Vs) in a 55-nm thick film that was almost thin enough to fully deplete the channel. The TFT using this Ge layer exhibited both high μFE (170 cm2/Vs) and on/off current ratios (∼102). This is the highest μFE among low-temperature (<500 °C) polycrystalline Ge TFTs without minimizing the channel region (<1 μm).

High-Mobility Ge pMOSFETs With Crystalline ZrO2 Dielectric

High-mobility Ge pMOSFETs with crystalline ZrO2 gate dielectric are realized and compared against devices with O3/ZrO2, amorphous ZrO2, and Al2O3/ZrO2 gate dielectrics. The crystallization of ZrO2provides for significantly improved effective hole mobility ( $\boldsymbol {\mu }_{\textsf {eff}}$ ) and reduced capacitance equivalent thickness (CET), boosting the transistor drive current. An interfacial Al2O3 passivation layer enhances $\boldsymbol {\mu }_{\textsf {eff}}$ but increases the CET. Passivation-free Ge pMOSFETs with 2.5-nm crystalline ZrO2gate dielectric achieve a higher $\boldsymbol {\mu }_{\textsf {eff}}$ than previously reported unstrained Ge pMOSFETs with the CET below 1 nm, at a high inversion-layer charge density.

Fabrication of Ge MOS with low interface trap density by ALD of Al2O3 on epitaxially grown Ge

Effects of initial surface conditions on interface characteristics of Al2O3/GeOx/Ge gate stacks are studied. As a clean surface condition prior to atomic layer deposition (ALD), a non-terminated Ge surface is realized by the insertion of an epitaxial Ge layer are grown on a Ge substrates in a MBE chamber which is directly connected to an ALD chamber. For these structures, the fixed charge density (Qf) and interface trap density (Dit) are evaluated from the C-V characteristics and conductance method. Qf reduction of about 17% and 90% are achieved by insertion of the epi-Ge layer and additional GeOx formation using plasma post-oxidation, respectively. A 90% reduction of Dit is also confirmed. These results indicate the importance of the initial Ge surface conditions before ALD and the Al2O3/GeOx/Ge gate stacks are very promising for high mobility Ge based CMOS applications.

(Keynote) Interface Control for High Performance N-Channel Ge FETs

The demonstration of high electron mobility Ge n-MOSFETs was not an easy task. To overcome such big challenge, three carrier scattering mechanisms in Ge MOS inversion layer such as Coulomb scattering, phonon scattering, and surface roughness scattering were carefully investigated. The first step was to improve the peak electron mobility by reducing the interface states density (Dit ). We succeeded in the reduction of Dit (<1011 eV-1cm-2) at Ge/GeO2 interface by employing the high-pressure O2 (HPO) oxidation [1]. This is quite reasonable thermodynamically [2]. However, there still remained two critical challenges. One was how to suppress the significant degradation of high-Ns electron mobility. The other one was how to keep electron mobility high in thin EOT region [3]. It is generally considered that high-Ns electron mobility is dominated by the interface roughness scattering. Since we demonstrated that Ge(111) was the best surface orientation for electrons to achieve the highest peak electron mobility, we challenged to realize the atomically flat Ge(111) surface by using H2 annealing [4]. Then, MOSFETs on Ge(111) with and without atomically flat surface were fabricated with HPO. N-channel MOSFETs fabricated by HPO on atomically flat Ge(111) exhibited greatly improved high-Ns electron mobility [5]. EOT reduction was also challenging because HPO should naturally form thicker GeO2. This fact was a big hurdle on Ge FET technology. Meanwhile, it was interestingly found that the low-temperature HPO (LT-HPO) reduced the oxidation rate [6]. This fact enabled us to achieve ~2 nm EOT GeO2 on Ge with superior interface and bulk GeO2. Another way to reduce EOT is obviously to replace HPO-GeO2 with other high-k oxides which are appropriate for Ge. We have fortunately found that Y2O3 is very friendly with Ge [7]. Furthermore, in our recent experiments Y2O3-doped GeO2 (YGO) is much better than pure Y2O3 on Ge. Significantly improved electron mobility in n-channel Ge FETs in a wide range of electron density has been achieved, when YGO in addition to H2 annealing has been used for the interfacial layer in gate stacks [8]. Poor electron mobility in n-channel Ge FETs is not true now. We can engineer the Ge interface through understanding of thermodynamics in gate stack formation and of kinetics of both surface planarization and oxidation. Thus, we can safely conclude that Ge is very promising not only for p-channel but also for n-channel FETs.

Fabrication of asymmetric Ge Schottky tunneling source n-channel field-effect transistor and its characterization of tunneling conduction

An asymmetric Schottky tunneling source field-effect transistor (STS FET) is a prospective device structure to suppress the short channel effect and to reduce the off-state current. An obstacle to implement a STS FET with a high mobility Ge channel was to form a metal/Ge contact with a low electron barrier height (ΦBN). Recently, we succeeded in the fabrication of a TiN/Ge contact with an extremely low ΦBN. In this study, a Ge-STS n-channel FET was fabricated, here PtGe/Ge and TiN/Ge contacts were used as the source and the drain. The device showed well-behaved transistor operation. From the current-voltage measurements in the wide temperature range of 160–300K, the conduction mechanism from the source to the channel is confirmed to be field emission tunneling. This result will be the first step toward achieving a high-performance Ge-STS n-FET.

(Invited) Monolithic Integration of n-In0.53Ga0.47As and p-Ge FinFETs on Si

With continuous increase in transistor count and clock frequency, the power density of current Si integrated circuits has reached a level that calls for a revolutionary change in transistor technology. High hole mobility Ge and high electron mobility InGaAs have been considered to be the most promising channel materials for p-channel and n-channel MOSFETs, respectively. Selective-area growth (SAG) on nano-trenches has been quite popular in integrating III-V materials with Si substrates. Since there exists a high lattice mismatch between III-V materials and Si, obtaining defect-free epilayer is still a great challenge. In this work, we demonstrate selective area growth of InGaAs on Ge trenches aiming at integrating n-channel InGaAs FinFETs and p-channel Ge FinFETs side by side on a Si substrate for CMOS applications. The Ge templates, which were grown on Si by chemical vapor deposition, were prepared by etching through an oxide mask using a dilute H2O2 solution to create Ge linear trench structures with embedded {111} facets at the bottom of the trenches for facilitating the regrowth of III-V materials. The III-V materials were selectively grown on the patterned Ge templates by metal-organic vapor phase epitaxy. An InGaP buffer layer, which has a wide bandgap and is beneficial for electrical isolation between the channel and substrate, was grown onto the Ge trenches. Undoped InGaAs was grown on InGaP as the n-channel material. High resolution transmission microscopy investigations show that very few dislocations are present near the Ge/InGaP interface in the trenches. It is found that In content of InGaP increases from 50 % to about 70 % with growth as evidenced by energy-dispersive x-ray spectroscopy (EDX). Interestingly, composition grading is also observed on the subsequently grown InGaAs. It begins from an In0.21Ga0.79As layer, which has good lattice match to the In0.7Ga0.3P layer beneath, then changes to the nominal In0.71Ga0.29As layer near the top of the fin. The strain in InGaAs is partially released through the generation of dislocations near the InGaAs/InGaP interface, leading to a nearly defect-free region at the top of the fin. A growth mechanism is proposed to account for the correlation between strain accommodation, composition grading, and defects generation.

(Invited) Unseeded Growth of Poly-Crystalline Ge with (111) Surface Orientation on Insulator by Pulsed Green Laser Annealing

Thin-film transistors (TFTs) with a high channel mobility for both electrons and holes are required for the three-dimension large scale integrations or system-on-panels. Lower temperature process is more favorable for TFT fabrication because the application of plastic substrate to system-on-panels is expected to add the flexibility function. Germanium (Ge) has higher hole and electron mobilities than Si, suggesting that large-grain poly-crystalline or single-crystalline Ge thin films lead to high channel mobility TFTs. This paper describes unseeded growth of poly-crystalline Ge with well-oriented large-size grains on insulator from amorphous Ge by scanning pulsed green laser annealing. In experimental, a 50-nm-thick amorphous Ge layer was deposited on a Si substrate with a 50-nm-thick SiO2 film. The Ge layer was patterned to narrow stripes of 2-µm-width. Then a capping layer of 650-nm-thick SiO2 was deposited. For this processed template, a scanning pulse green laser annealing was performed. Q-switch Nd:YAG laser beam with the following properties was used for annealing; a Gaussian line beam of 70 x 1400 µm2 at a laser wavelength of 532 nm, a pulse frequency of 7.5 kHz, a scanning velocity of 150 µm/s, and energy densities from 0.5 to 0.7 J/cm2. The Ge stripes were crystallized by a single scanning, where the beam was scanned perpendicular to the longitudinal direction of the beam. The Ge stripes crystallized at the optimum energy of 0.56 J/cm2 by the scanning pulsed laser annealing was characterized by electron back scattering diffraction patterns (EBSD). The EBSD mapping of normal direction to the sample surface indicates that the crystallized Ge film has (111) surface orientation in the 600 µm-long stripe. The (111) Ge crystal begins within only 2 µm after the starting point of the laser scanning. It was observed that the crystal orientation was recovered to (111) even if the prior part of crystalized Ge film was rotated from (111) surface. In the mapping of rolling direction, which corresponds to the laser scanning direction, two types of grains are dominant. One shows (101) and the other shows (112) for the laser scanning direction. From the normal direction and rolling direction images of EBSD, the Ge stripes were crystallized with the grains of 2 µm wide and ~10 µm long. The maximum grain length of 20 µm was also observed. Raman scattering was measured to evaluate the crystalline quality of the (111) surface-oriented Ge stripes. The full-width at half-maximum of 2.35 cm-1 shows good crystal quality of the film, which is smaller than the values of 3.2-3.3 cm-1 for the single crystalline Ge film obtained by lateral liquid-phase epitaxy from a Si seed. For laser fluence dependence, Ge stripes were not crystallized when the fluence was smaller than 0.56 J/cm2, and Ge stripes show non-oriented crystal with a long grain boundary in the center of stripe width when the fluence was larger than 0.67 J/cm2. Simulation analyses of thermal diffusion reveal the crystallization process. The pulse laser irradiation heats the Ge stripe and melts it. Simultaneously the underlying Si in the outside region of the Ge stripe patterns absorbs the laser energy and is also heated up. During the cooling period after each pulse a temperature gradient between the edge and the center is produced in the molten Ge stripe, because of suppression of cooling at the edge. Then the temperature at the center of the Ge stripe drops below the solid point first rather than the center. Crystal growth occurs from the center to the edges, resulting that random nucleation at the edge is suppressed and crystal growth proceeds with controlled orientation in the Ge stripe. This crystallization method is promising to realize high-mobility (111) Ge TFTs and easily extended to the glass or plastic substrate by making amorphous Si layer, which works as a laser absorbing layer, and SiO2, which works as a heat insulating layer, on the substrate.

The achievement of the super short channel control in the magnetic Ge n-FinFETs with the negative capacitance effect

Super short channel control (sub-threshold swing = 95 mV/dec) in Ge n-type Fin Field-Effect Transistors (n-FinFETs) is achieved through the promising gate stack characteristics of gate leakage (Jg)-equivalent-oxide-thickness (EOT) and ultra-high k-value (∼312) with the implement of the magnetic gate stack scheme. On the other hand, the negative capacitance effect is also observed in the magnetic Ge n-FinFETs by the extraction of the body factor (m = 0.47) at low temperature measurement. The proposed magnetic gate stack scheme (tetragonal-phase BaTiO3 as the dielectric layer and magnetic FePt film as the metal gate) in the Ge n-FinFETs has super Jg-EOT characteristics, negative capacitance phenomenon, and promising transistor performance. It provides the useful solution for the future low power mobile devices designed on the high mobility (Ge) material.

Junctionless Gate-All-Around pFETs Using &lt;italic&gt;In-situ&lt;/italic&gt; Boron-Doped Ge Channel on Si

Junctionless devices exhibit favorable $I_{{\rm on}}/I_{{\rm off}}$ and SS in high-mobility Ge channels owing to the elimination of junction leakage. With channel doping of 5 × 1018 cm−3, the fin width of 27 nm and the gate length of 250 nm, our gate-all-around device has the $I_{{\rm on}}/I_{{\rm off}}$ of 1 × 106, the SS of 95 mV/dec, and the $I_{{\rm on}}$ of 275 μA/μm. The drain current reaches 390 μA/μm for the device with channel doping of 8 × 1019 cm−3, and the fin width of 9 nm. The junctionless devices show higher mobility in the large $V_{{\rm GS}} -V_{T}$ region than the inversion mode devices due to less dependence on surface roughness scattering. Junctionless devices also show increasing drive current at increasing temperatures due to the nature of impurity scattering.

The demonstration of promising Ge n-type multi-gate-field-effect transistors with the magnetic FePt metal gate scheme

In this work, the tetragonal-phase BaTiO3 high dielectric (HK) layer and the magnetic FePt metal gate (MG) film are proposed to be the gate stack scheme on the Ge three dimensional (3D) n-type multi-gate-field-effect transistors (FETs). The ∼75% dielectric constant (κ-value) improvement, ∼100× gate leakage (Jg) reduction, and ∼70% on-state current (Ion) enhancement are achieved due to the colossal magneto-capacitance effect. The magnetic field from the magnetic FePt MG film couples and triggers more dipoles in the BaTiO3 HK layer and then results in the super gate stack characteristics. The promising transistor's performance (∼200 μA/μm on the device with the gate length Lch = 60 nm) on the high mobility (Ge) material in the 3D n-type multi-gate-FETs device structure demonstrated in this work provides the useful solution for the future advanced logic device design.

(Invited) Smartphones: Driving Technology to More than Moore 3-D Stacked Devices/Chips and More Moore FinFET 3-D Doping with High Mobility Channel Materials from 20/22nm Production to 5/7nm Exploratory Research

Today smartphone ICs are driving technology to More Moore 3-D device scaling and More Than Moore 3-D stacked devices with >1.24B smartphones sold in 2014 accounting for >27% of all ICs. The expected increase in smartphone application processor (AP) demand in 2015 (Samsung Exynos 7 for Galaxy S6 and Apple A9 for iPhone 6s/7) is driving the rapid ramp to 14/16nm technology node 3-D FinFET devices at foundries, 3-D memory devices such as 128Gb NAND Flash memory devices with 32-layers and 3-D stacked chips for form factor with >40% package area saving. Intel was first to production with 3-D bulk-FinFET devices at the 22nm technology node in 2011 and reported their SOC version for Chinese low-end smartphone market. Intel’s 2nd generation bulk-FinFET devices at 14nm node was introduced in Aug 2014 with their SOC version to follow. In Sept 2012 iPhone 5 was first to incorporate Sony’s 8M pixel 3-D stacked backside CMOS image sensor for rear-facing camera. In April 2015 Samsung Galaxy S6 incorporated 14nm technology node 3-D FinFET devices in the Exynos 7 Octa application processor and first 3-D ePOP (embedded package on package) which stacks AP+DRAM (3Gb LPDDR3)+Flash(128/64/32Gb)+eMMC (embedded multi-media card)+controller saving 40% area and use Sony’s 16M pixel 3-D stacked back-side CMOS image sensor for rear-facing camera and 5M pixel RWB image sensor for front-facing camera. Apple will introduce the iPhone 6s/7 in Sept 2015 with A9 application processor using 3-D FinFET devices with Samsung/Foundry 14nm technology node and TSMC 16FF+. 10nm technology node is expected in 2016 with higher mobility SiGe or Ge channel material then 7nm node in 2018 and gate-all-around nano-wire by 5nm node in 2020. To understand 3-D FinFET doping and high mobility channel material this paper will first review the current doping and Fin/channel mobility enhancement techniques used for 22nm FinFET production by Intel for both high performance logic and SOC devices and the changes they made for their 2nd generation 14nm FinFET. 3-D 8o tapered FinFET S/D extension conformal doping was achieved with high tilt ion implantation at >45 degree. Highest retained dose and improved Fin sidewall line-edge-roughness (LER) on the atomic level can be realized with Hydrogen annealing surface passivation. High dopant activation is also achieved with advanced annealing SPE techniques of amorphous implanted junctions. Other 3-D dopant methods such as plasma implantation, knock-in dopant and deposition doping with diffusion including monolayer doping were not successful due to poor dopant activation and severe surface dopant loss. FinFET channel mobility enhancement at 22nm node used (511) plane taper Fin with 55% eSiGe S/D compressive strain for PMOS and amorphous implant SPE residual stacking fault defect S/D tensile stressor for NMOS. For 14nm node taller vertical Fins without the (511) taper and still 55% eSiGe S/D for PMOS and now eS/D for NMOS which is full of stacking fault defects. At the 10nm or 7nm node direct higher mobility Fin/channel material (SiGe, Ge or III-V) is expected to be introduced followed by exploratory research of gate-all-around nanowire for 5nm technology node. 25% SiGe to 100% Ge high mobility Fin-channel material on Si wafers will be realized by traditional gas/vapor phase epitaxial growth techniques by chemical vapor deposition (CVD) in blanket, selective growth including aspect ratio trapping, Ge condensation or an alternative liquid phase epitaxial (LPE) regrowth of an amorphous material layer by melt solidification. At 5nm node Si, SiGe or Ge nano-wire gate-all-around devices. Finally a discussion on dopant activation in high mobility Ge and SiGe material with low junction leakage.

(Invited) Opportunities of High Performance Ge CMOS

Ge is not a new material but now spotlighted for beyond Si-scaled CMOS. Ge p-MOSFETs have been well investigated and its high performance has so far been demonstrated. On the contrary, an achievement of high electron mobility Ge n-MOSFETs is quite challenging due to a large amount of interface states near the conduction band edge. So, we first discuss how to overcome “intrinsic challenges in Ge n-MOSFETs” from thermodynamic viewpoint of GeO2 on Ge. A very low Dit (<1011 eV-1cm-2) at Ge/GeO2 interface and a very high peak electron mobility in Ge n-MOSFETs are presented. This is further extended to scaled gate stacks on Ge by controlling the oxygen potential of dielectric films on Ge.

Ge nanobelts with high compressive strain fabricated by secondary oxidation of self-assembly SiGe rings

Curled Ge nanobelts were fabricated by secondary oxidation of self-assembly SiGe rings, which were exfoliated from the SiGe stripes on the insulator. The Ge-rich SiGe stripes on insulator were formed by hololithography and modified Ge condensation processes of Si0.82Ge0.18 on SOI substrate. Ge nanobelts under a residual compressive strain of 2% were achieved, and the strain should be higher before partly releasing through bulge islands and breakage of the curled Ge nanobelts during the secondary oxidation process. The primary factor leading to compressive strain is thermal shrinkage of Ge nanobelts, which extrudes to Ge nanobelts in radial and tangent directions during the cooling process. This technique is promising for application in high-mobility Ge nano-scale transistors.

Liquid Phase Epitaxy (LPE) Formation of Localized High Quality and Mobility Ge & SiGe by High Dose Ge-Implantation with Laser Melt Annealing for 10nm and 7nm Node CMOS Technology

We investigated using high dose (5E16/cm2) Ge beam-line ion implantation in combination with laser melt annealing as an alternative to Ge-epi by CVD to form high quality single crystal Ge-epilayer by LPE (liquid phase epitaxy) that is very uniform, thin 10-25nm and localized for high mobility Ge-channels. The implant resulted in 7nm amorphous Ge deposition by a method called dose controlled deposition (DCD). A 515nm laser was used to vary the melt depth from 9nm to 500nm based on laser anneal pulse duration and power level. Ellipsometer was used to measure the surface amorphous layer thickness while therma-wave (TW) analysis was used to monitor Ge implant damage recovery after LPE. SIMS depth profiles showed Ge surface concentration varied from 100% down to 2% based on the laser melt depth. X-TEM analysis showed the transformation of deposited amorphous Ge surface layer to single crystal Ge after laser melt and LPE. Sb implantation at two dose levels of 3E15/cm2 and 3E13/cm2 was used to examine laser melt annealing effects on n-type dopant activation and electron mobility in Ge. Special Hx-probe tips on the 4PP system was required to measure sheet resistance and CAOT/DHE method was used for Differential Hall Effect measurements.

Liquid Phase Epitaxy (LPE) Formation of Localized High Quality and Mobility Ge & SiGe by High Dose Ge-Implantation with Laser Melt Annealing for 10nm and 7nm Node CMOS Technology

Localized Ge and SiGe high quality/mobility device surface material region on bulk-Si and SOI wafers are needed for 10nm and 7nm node CMOS technology. Traditionally SiGe and Ge device surface material on bulk-Si or SOI wafers are realized by CVD epitaxial growth or Vapor Phase Epi (VPE) at elevated temperatures. Selective deposition can be achieved with hard mask. To reduce defects strain relaxed buffer (SRB) or aspect ratio trapping (ART) have been employed with bulk-Si or layer transfer wafer bonding for SiGeOI or GeOI. An alternative to VPE is to use either SPE (solid phase epitaxy) or LPE (liquid phase epitaxy) to form SiGe or Ge epitaxial surface layers. Using high dose Ge implantation >E16/cm2 with photoresist soft mask as proposed in 2004 by Borland et al [1,2]. Localized amorphous Ge surface regions can be formed after Ge-infusion doping by Gas Cluster Ion Beam (GCIB) technique followed by low temperature SPE to form single crystal thin surface Ge epitaxial layers but residual end-of-range (EOR) damage remained. Today, laser melt annealing of implanted junctions are currently being used in production for high quality back-side illuminated CMOS image sensors used in smart phone cameras by several IC and foundry semiconductor manufacturers to completely eliminate any residual implant damage/defects with 100% dopant activation provided the melt depth exceeds the implant damage depth [3]. Last year at IWJT-2013 Borland et al [4] reported using Ge-plasma ion implantation at 1E16/cm2 and 1E17/cm2 doses with laser melt annealing to realize up to 55% SiGe by LPE with >4x higher mobility at 160cm2/Vs. One limitation they noted with plasma implantation was poor retained dose due to surface sputtering at low energies which limited the Ge content to <55% for 1E17/cm2 dose. Therefore to overcome this retained dose problem we investigated Ge beamline ion implantation in this paper which should give 100% retained dose. The Ge surface amorphous layer thickness measured by elipsometry was 15nm while the Ge-SIMS depth profile measures 7nm Ge at 100%. Therma-wave analysis was used to monitor the Ge-implant damage recovery and Ge or SiGe recrystallized epitaxial surface layer after various laser melt annealing conditions of varying power level and pulse duration. The Ge-SIMS depth profiles shows we could vary the melt depth for LPE Ge layer from 10nm to >400nm and the Ge layer content from 97% down to 2% respectively. We will also show X-TEM of the Ge-LPE regions. Sb implantation was used to investigate n-type dopant activation in Ge at low and high doses of 3E13/cm2 and 3E15/cm2. Rs measurements were done using a special Hx 4 point probe and SRP (spreading resistance profile) depth profiles. In summary, using high dose beam-line Ge-implantation we realized >7nm amorphous Ge deposition. Epitaxial growth of Ge was achieved by liquid phase epitaxy using shallow laser melt annealing between 10nm and >400nm melt depths.