High-level Synthesis System Research Articles

High-level synthesis in an industrial environment

The use of modern hardware-description languages in the chip design process has allowed designs to be modeled at higher abstraction levels. More powerful modeling styles, such as register-transfer and behavioral level specifications, have spurred the development of high-level synthesis techniques in both industry and academia. However, despite the many research efforts, the technology is not yet in widespread use in industry. This paper presents the IBM High-Level Synthesis System (HIS), which is the first such system to be used in production in IBM. HIS synthesizes gate-level networks from VHDL models at various levels of abstraction. The main algorithms, modeling capabilities, and methodology considerations in the HIS system are presented. Results show that HIS is capable of producing implementations comparable to or better than those of the existing methodology, while shortening the design time significantly. The HIS system is currently in production use and evaluation in several IBM sites for processors and peripheral chip designs, as well as being an external commercial product.

Optimizing power using transformations

The increasing demand for portable computing has elevated power consumption to be one of the most critical design parameters. A high-level synthesis system, HYPER-LP, is presented for minimizing power consumption in application specific datapath intensive CMOS circuits using a variety of architectural and computational transformations. The synthesis environment consists of high-level estimation of power consumption, a library of transformation primitives, and heuristic/probabilistic optimization search mechanisms for fast and efficient scanning of the design space. Examples with varying degree of computational complexity and structures are optimized and synthesized using the HYPER-LP system. The results indicate that more than an order of magnitude reduction in power can be achieved over current-day design methodologies while maintaining the system throughput; in some cases this can be accomplished while preserving or reducing the implementation area. >

Verifying a logic-synthesis algorithm and implementation: a case study in software verification

We describe the verification of a logic synthesis tool with the Nuprl proof development system. The logic synthesis tool, Pbs, implements the weak division algorithm. Pbs consists of approximately 1000 lines of code implemented in a functional subset of Standard ML. It is a proven and usable implementation and is an integral part of the Bedroc high level synthesis system. The program was verified by embedding the subset of Standard ML in Nuprl and then verifying the correctness of the implementation of Pbs in the Nuprl logic. The proof required approximately 500 theorems. In the process of verifying Pbs we developed a consistent approach for using a proof development system to reason about functional programs. The approach hides implementation details and uses higher order theorems to structure proofs and aid in abstract reasoning. Our approach is quite general, should be applicable to any higher order proof system, and can aid in the future verification of large software implementations. >

Integration of medium-throughput signal processing algorithms on flexible instruction-set architectures

Integrated circuits in telecommunications and consumer electronics are rapidly evolving towards single chip solutions. New IC architectures are emerging, which combine instruction-set processor cores with customised hardware. This paper describes a high-level synthesis system for integration of real-time signal processing systems on such processor cores. The compiler supports a flexible architectural model. It can handle certain types of incompletely specified architectures, and offers capabilities for retargetable compilation and architectural exploration. Results for a realistic application from the domain of audio processing indicate the feasibility and power of the presented approach.

Partial scan design of register-transfer level circuits

Register-transfer level designs that are derived from high-level synthesis systems generally consist of functional blocks and registers that are interconnected by multiplexers and buses to maximize resource sharing These multiplexer and bus structures have the unique ability to behave asswitches, i.e., to logically partition the circuit when their control inputs are manipulated in different ways. The presence of switches, the selection of scan registers can be influenced. This leads to an efficient partial scan methodology presented in this paper. Second, switches help set up data transfer paths calledI-paths. By employingI-paths to transport test data, the functional logic in the circuit can be separated from the switching logic for the purpose of test generation. This can lead to a reduction in test generation costs for a partial scan design. Thus the techniques presented in this paper help to minimize both testability overhead and test generation cost in bus-based circuits. This methodology is implemented in the SIESTA system for serial scan design.

Towards amalgamating high-level synthesis and proof systems

This paper gives an overview of an ongoing research project on the application of formal methods to high-level synthesis. The key idea is to embed a design representation used in an existing high-level synthesis system in a mechanical proof system. This approach has the following properties: First, we use a design representation proved applicable to high-level synthesis; Second, we can reason about design transformations used in an existing high-level synthesis system; Third, we allow formal reasoning about both control and data; and Fourth, we provide mechanical support for formal reasoning.

The Siemens high-level synthesis system CALLAS

The Siemens high-level synthesis system CALLAS

Exploiting the special structure of conflict and compatibility graphs in high-level synthesis

Coloring of conflict graphs and clique partitioning of compatibility graphs have been used in high-level synthesis to map operators, values, and data transfers onto shared resources. However, finding a minimum sized coloring or clique partition is NP hard. One method to overcome this complexity is to identify special types of graphs that can be colored or clique partitioned in polynomial time. Existing high-level synthesis systems have exploited two special types of conflict graphs-interval and circular-arc graphs. However, they have provided no insight into why and how frequently these graphs occur. This paper will investigate the features of behavioral representations and synthesis algorithms that give rise to special conflict and compatibility graphs. We will identify two additional types of graphs useful for high-level synthesis-chordal and comparability graphs-and demonstrate their use in an existing high-level synthesis system.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

Clairvoyant: a synthesis system for production-based specification

This paper describes a new high-level synthesis system based on the hierarchical production based specification (PBS). Advantages of this form of specification are that the designer does not describe the control flow in terms of explicit states or control variables, and that the designer does not describe a particular form of implementation. The production-based specification also separates the specification of the control aspects and data-flow aspects of the design. The control is implicitly described via the production hierarchy, while the data-flow is described as action computations. This approach is a hardware analog of popular software engineering techniques. The Clairvoyant system automatically constructs a controlling machine from the PBS and this process is not impacted by the possibly exponentially larger deterministic state space of the designs. The encodings generated by the constructions compare favorably to encodings derived using graph-based state encoding techniques in terms of logic complexity and logic depth. These construction techniques utilize recent advances in BDD techniques. >

A generic hardware architecture to support the system level synthesis of digital systems

A generic hardware architecture, which is the target for a system level VLSI synthesis system, is described in this paper. The specification of a real-time control system is defined, in the language BEADLE, as a logical network of concurrently active sequential tasks, which synchronise in order to communicate. The architecture was designed to implement such specifications using a number of node processors — one per task — interconnected via a customised communications network. The novelty of this approach is that the generic architecture is personalised by a high-level synthesis system for an application. The resulting hardware architecture is defined in VHDL, and is used as an input to lower-level physical synthesis tools. The relationship between the BEADLE language and the generic architecture is described, together with details of how the architecture is customised for specific applications. A critical appraisal of the prototype architecture is presented and future directions discussed.

Automated transformation of algorithms into register-transfer level implementations

This paper describes a high-level synthesis system, called CAMAD, for transforming algorithms into hardware implementation structures at register-transfer level. The algorithms are used to specify the behaviors of the hardware to be designed. They are first translated into a formal representation model which is based on timed Petri nets and consists of separate but related descriptions of control and data path. The formal model is used as an intermediate design representation and supports an iterative transformation approach to high-level synthesis. The basic idea is that once the behavioral specification is translated into the initial design representation, it can be viewed as a primitive implementation. Correctness-preserving transformations are then used to successively transform the initial design into an efficient implementation. Selection of transformations is guided by an optimization strategy which makes design decisions concerning operation scheduling, data path allocation, and control allocation simultaneously. The integration of these several synthesis subtasks has resulted in a better chance to reach the globally optimal solution. Experimental results show that our approach produces improved register-transfer designs, especially in the cases when the designed hardware consists of data paths and control logics that are tightly coupled.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

Global hardware synthesis guided by realistic probability computation

Probability computation is a technique used in some popular high-level synthesis systems, but important considerations (library of modules, concurrency of operators, hardware reusability, etc.) are not usually taken into account. We present an elaborate computation of realistic probabilities, and its application to a design space bounding strategy. Results show that computed probabilities and bounding strategy are good.

Synthesis for testability by synthesis controlling

The Synthesis for Testability system Synthesis Controller SC is described in this paper. SC integrates Design for Testability in usual High-Level Synthesis systems during the design process by controlling the synthesis phases. Symbolic assignments containing elements of a data flow graph are computed by the SC. The methods for the selection of the elements and the construction of the assignments are defined. The results and data structures of a High-Level Synthesis system are transformed based on the assignments. After integration of the modified results and data structures the synthesis process constructs a better testable design. The addition of the SC to an existing High-Level Synthesis system has led to designs of well integrated test concepts.

A system for production use of high-level synthesis

High-level synthesis has been an active research field since the early eighties. However, apart from a few exceptions the technology has so far failed to make a smooth transition into the industrial environment. The main reasons are related more to the lack of an integrated methodology, including design entry, simulation, and synthesis, than to the quality of the synthesis algorithms. Experiences in applying the HIS system (High-level IBM Synthesis System) to real designs led to the development of a system and methodology which integrate language modeling, simulation, high-level, and logic synthesis. This paper presents the main concepts behind this system, namely, its modeling, synthesis, and simulation capabilities. Moreover, it addresses some of the problems encountered when transferring high-level synthesis to a production environment.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

Rapid estimation for parameterized components in high-level synthesis

An important benefit of high-level synthesis is rapid design space exploration through examination of different design alternatives. However, such design space exploration is not feasible without fast and accurate area and delay estimates of the synthesized designs. These estimates must factor in physical design effects and technology-specific information in order to achieve accuracy. High-level synthesis tools often use abstract, parameterized component generators for describing the synthesized RT design, and thus need to be supported by fast and accurate estimators for these parameterized RT-components. Ideally, one would like to obtain the actual area and delay attributes of each component by constructing (or generating) the designs. However, such constructive methods require excessive run times, prohibiting on-line integration with the tasks of scheduling and allocation. This paper describes a fast (constant-time) method for estimating the area and delay of regular-structured generic RT components that are tuned to a particular technology library. The estimation models are generated using a least-square approximation on a set of sample data points from selected component implementations. The authors performed an extensive set of experiments to validate the estimation technique on combinational as well as sequential RT component generators. The results show a prediction of the area and delay to within 10% of the actual values. These models have also been integrated with a high-level synthesis system to permit on-line estimation of a component's area and delay. >

The Siemens high-level synthesis system CALLAS

In this paper we present the Siemens high-level synthesis system CALLAS and describe its design methodology and synthesis strategy. It supports the synthesis of control-dominated applications and uses a VHDL subset for the algorithmic specification. Its main feature can be characterized as "What you simulate is what you synthesize." This principle permits a validation of the synthesis results by simulation or even formal verification. CALLAS has been successfully applied on real designs which were implemented in silicon. These examples demonstrate that CALLAS fulfils the constraints and objectives of a hardware designer. The circuits are comparable in quality to results achieved by synthesis starting at the register-transfer-level.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

Formal analysis of correctness of behavioral transformations

Much has been said about the importance of formal verification in hardware synthesis, but little has been done. Where it has been applied at all, it has only been used on simple, idealized examples. This paper describes the application of formal semantic analysis and verification to part of a working high-level synthesis system. The process revealed several significant errors in that system, errors that had previously been undetected. This experience leads to some reflections on the need for a rigorous, formal basis for hardware specification and synthesis, and on the value of formal techniques.

Digital system simulation with VHDL in a high-level synthesis system

This paper presents the use of VHDL to simulate the intermediate design representation in a high-level synthesis system. The design representation is captured by an extended time Petri net notation and is used throughout the synthesis process. We have developed an algorithm to convert the design representation into a VHDL description. As a result, digital system designs can be simulated together with the behavioral models of the primitive register-transfer level components which are also described in VHDL. The main feature of our approach is that the intermediate results (as well as the final results) of the high-level synthesis process can be simulated at any time and the simulation results can be used to guide the synthesis process.

Optimizing the control-unit through the resynchronization of operations

Most approaches to control-unit optimization use a finite state machine model, where operations are bound to control states. However, when synthesizing circuits from a higher, more abstract level of hardware specification that supports concurrency and synchronization, these approaches may be overly restrictive. We present a strategy for optimizing control circuits based on resynchronization of operations such that the original specification under timing constraints is still satisfied but with a lower control implementation cost. We use a general constraint graph model to capture the high level specification; the model supports unbounded delay operations, detailed timing constraints, and concurrency. We introduce the notion of synchronization redundancy and formulate the optimization problem as the task of mapping operations to synchronization points. We present algorithms to find a minimal control cost implementation. Results of applying the technique within the framework of the Hercules/Hebe High-level Synthesis system are presented.

Silicon compilation and rapid prototyping of microprogrammed VLSI-Circuits with MIMOLA and SOLO 1400

We describe the MIM2SOLO Silicon Compiler which integrates the MIMOLA high-level synthesis system and the SOLO 1400 standard-cell IC design system. Key features of the system are synthesis from an algorithmic description, full simulation support with automatic test pattern generation, and support of hybrid (analogue/digital) designs. We present a CISC processor designed both traditionally and using MIM2SOLO and compare design efforts and layout. As an example of hybrid designs, we discuss a digital filter with on-chip analogue-digital and digital-analogue converters.