High-level Synthesis Methodology Research Articles

Power Optimization With Power Islands Synthesis

With the migration to deep sub-micron process technologies, the power consumption of a circuit has come to the forefront of concerns, and as a result, the power has become a critical design parameter. This paper presents a novel high-level synthesis methodology, called Power Islands Synthesis, that eliminates the spurious switching activity and the leakage in a great portion of the resulting circuit by partitioning it into islands. Each island is a cluster of logic whose power can be controlled independently from the rest of the circuit and hence can be completely powered down when all of the logic it contains is idling. The partitioning is done in such a way that the components with maximally overlapping lifetimes are placed on the same island. By powering down an island during its idle cycles, the following occur: 1) The spurious switching that results from the broadcast to idle components is silenced and 2) the power consumption due to leakage in inactive components is eliminated. Experiments conducted on several synthesis benchmarks implemented at the layout level with a 65-nm process technology and simulated using a transistor-level simulator showed power savings ranging from 5% to 20% due to our methodology. The reported savings were entirely from the power down of combinational elements (functional resources) of the data path.

Scheduling of Iterative Algorithms with Matrix Operations for Efficient FPGA Design—Implementation of Finite Interval Constant Modulus Algorithm

This paper deals with the optimization of iterative algorithms with matrix operations or nested loops for hardware implementation in Field Programmable Gate Arrays (FPGA), using Integer Linear Programming (ILP). The method is demonstrated on an implementation of the Finite Interval Constant Modulus Algorithm. It is an equalization algorithm, suitable for modern communication systems (4G and behind). For the floating-point calculations required in the algorithm, two arithmetic libraries were used in the FPGA implementation: one based on the logarithmic number system, the other using floating-point number system in the standard IEEE format. Both libraries use pipelined modules. Traditional approaches to the scheduling of nested loops lead to a relatively large code, which is unsuitable for FPGA implementation. This paper presents a new high-level synthesis methodology, which models both, iterative loops and imperfectly nested loops, by means of the system of linear inequalities. Moreover, memory access is considered as an additional resource constraint. Since the solutions of ILP formulated problems are known to be computationally intensive, an important part of the article is devoted to the reduction of the problem size.

A Low Complexity and Low Power SoC Design Architecture for Adaptive MAI Suppression in CDMA Systems

In this paper, we propose a reduced complexity and power efficient System-on-Chip (SoC) architecture for adaptive interference suppression in CDMA systems. The adaptive Parallel-Residue-Compensation architecture leads to significant performance gain over the conventional interference cancellation algorithms. The multi-code commonality is explored to avoid the direct Interference Cancellation (IC), which reduces the IC complexity from \(\mathcal{O}(K^2N)\) to \(\mathcal{O}(KN)\). The physical meaning of the complete versus weighted IC is applied to clip the weights above a certain threshold so as to reduce the VLSI circuit activity rate. Novel scalable SoC architectures based on simple combinational logic are proposed to eliminate dedicated multipliers with at least \(10 \times\)saving in hardware resource. A Catapult C High Level Synthesis methodology is apply to explore the VLSI design space extensively and achieve at least \(4 \times\)speedup. Multi-stage Convergence-Masking-Vector combined with clock gating is proposed to reduce the VLSI dynamic power consumption by up to \(90 \%\)

Generation of distributed logic-memory architectures through high-level synthesis

With the increasing cost of on-chip global communication, high-performance designs for data-intensive applications require architectures that distribute hardware resources (computing logic, memories, interconnect, etc.) throughout the chip, while restricting computations and communications to geographic proximities. In this paper, we present a methodology for high-level synthesis (HLS) of distributed logic-memory architectures, i.e., architectures that have logic and memory distributed across several partitions in a chip. Conventional HLS tools are capable of extracting parallelism from a behavior for architectures that assume a monolithic controller/datapath communicating with a memory or memory hierarchy. This paper provides techniques to extend the synthesis frontier to more general architectures that can extract both coarse and fine-grained parallelism from data accesses and computations in a synergistic manner. Our methodology selects many possible ways of organizing data and computations, carefully examines the tradeoffs (i.e., communication overheads, synchronization costs, area overheads) in choosing one solution over another, and utilizes conventional HLS techniques for intermediate steps. We have evaluated the proposed framework on several benchmarks by generating register-transfer level (RTL) implementations using an existing commercial HLS tool with and without our enhancements, and by subjecting the resulting RTL circuits to logic synthesis and layout. The results show that circuits designed as distributed logic-memory architectures using our framework achieve significant (up to 5.3/spl times/, average of 3.5/spl times/) performance improvements over well-optimized conventional designs with small area overheads (up to 19.3%, 15.1% on average). At the same time, the reduction in the energy-delay product is by an average of 5.9/spl times/ (up to 11.0/spl times/).

Coordinated parallelizing compiler optimizations and high-level synthesis

We present a high-level synthesis methodology that applies a coordinated set of coarse-grain and fine-grain parallelizing transformations. The transformations are applied both during a pre-synthesis phase and during scheduling, with the objective of optimizing the results of synthesis and reducing the impact of control flow constructs on the quality of results. We first apply a set of source level presynthesis transformations that include common sub-expression elimination (CSE), copy propagation, dead code elimination and loop-invariant code motion, along with more coarse-level code restructuring transformations such as loop unrolling. We then explore scheduling techniques that use a set of aggressive speculative code motions to maximally parallelize the design by re-ordering, speculating and sometimes even duplicating operations in the design. In particular, we present a new technique called "Dynamic CSE" that dynamically coordinates CSE and code motions such as speculation and conditional speculation during scheduling. We implemented our parallelizing high-level synthesis in the <i>SPARK</i> framework. This framework takes a behavioral description in ANSI-C as input and generates synthesizable register-transfer level VHDL. Our results from computationally expensive portions of three moderately complex design targets, namely, MPEG-1, MPEG-2 and the GIMP image processing tool, validate the utility of our approach to the behavioral synthesis of designs with complex control flows.

A Reusable Smart Interface for Gas Sensor Resistance Measurement

The advances of the semiconductor industry enable microelectromechanical systems sensors, signal conditioning logic and network access to be integrated into a smart sensor node. In this framework, a mixed-mode interface circuit for monolithically integrated gas sensor arrays was developed with high-level design techniques. This interface system includes analog electronics for inspection of up to four sensor arrays and digital logic for smart control and data communication. Although different design methodologies were used in the conception of the complete circuit, high-level synthesis tools and methodologies were crucial in speeding up the whole design cycle, enhancing reusability for future applications and producing a flexible and robust component.

Resource Budgeting for Multiprocess High-Level Synthesis

This paper presents a new high-level synthesis methodology to generate optimized register-transfer level (RTL) implementations for multiprocess behavioral descriptions. The concurrent communicating processes specification paradigm is widely used in digital circuit and system design, and is employed in all popular hardware description languages. It has been shown that interprocess communication and synchronization can result in complex timing interdependencies, which significantly affect the performance of a multiprocess system. In this paper, we demonstrate that state-of-the-art high-level synthesis tools can generate significantly suboptimal implementations for behaviors that contain concurrent communicating processes. We present an analysis of how interprocess communication impacts high-level synthesis steps, and describe a new methodology to adapt existing high-level synthesis tools to optimize multiprocess descriptions. Our methodology is based on executing multiprocess performance analysis and process-by-process scheduling in an iterative manner. We present algorithms for key steps in the proposed methodology. We have performed extensive experiments in the context of a commercial high-level design flow to evaluate the proposed techniques. The results clearly demonstrate the utility of our techniques in synthesizing implementations with superior area, performance, and energy consumption. For example, up to 40% performance improvement (average of 35.6%) was achieved with little or no area overhead (average of 4.8%). In effect, the proposed techniques lead to a shift of the entire area-delay tradeoff curve for a design, to include superior designs that were hitherto infeasible. Our techniques also simultaneously result in up to 50% (average of 33.5%) improvement in energy and up to 69% (average of 58.3%) improvement in the energy-delay product.

Exploration-based high-level synthesis of linear analog systems operating at low/medium frequencies

This paper presents a methodology for high-level synthesis of continuous-time linear analog systems. Synthesis results are architectures of op-amps, sized resistors and capacitors such that their ac behavior and total silicon area are optimized. Bounds for op-amp dc gain, unity-gain frequency, input, and output impedances are found as a byproduct of synthesis. Subsequently, a circuit synthesis tool can be used to synthesize the op-amps of an architecture. The paper details the architecture generation technique. Architecture generation produces alternative architectures for a system specification using the tabu search heuristic. Its main advantages over traditional methods is that it is application independent, does not require a library of block connection patterns, and is simple to implement. The paper also discusses the hierarchical, two-step parameter optimization that guides architecture generation. Experiments showed that linear analog systems operating at low/medium frequencies (like telecommunication systems and filters) can be synthesized in a reasonably long time and with reduced effort.

Low Power Synthesis Methodology with Data Format Optimization Applied on a DWT

In modern VLSI circuits, power consumption has become a design criteria as well as speed and silicon area or gate count. To guide the designer implementing complex applications with real time constraint on dedicated circuits, we present a High Level Synthesis methodology that provides a Register Transfer Level description of an ASIC, from a behavioral description of an algorithm; this complete methodology uses basic techniques such as selection, assignment or scheduling specified for power optimization, associated with a new approach based on data format optimization. Actually, instead of the usual 32-bit floating-point format, it is power efficient to use a fixed-point format provided overflow and computation noise problems are solved. The application of our method on an usual DSP example (the DWT) shows a power reduction of more than 60%.

Analogue and Mixed-Signal Systems Topologies Exploration Using Symbolic Methods

This paper describes the use of symbolic methods applied to the automatic exploration and characterisation of analogue and mixed-signal systems topologies and architectures. The developed methodology acquires the desired system requirements at the algorithm-level, using an HDL description, and employs, both, a modified signal flow graph approach and a pattern recognition techniques for synthesis purposes, leading to a complete characterisation of the sub-blocks from the automatically generated architecture. Thus, by allowing the synthesis process to move into higher levels of abstraction, the proposed methodology provides a computer-based framework for the systematic and uniform treatment of various types of data conversion systems, including the search for new conversion algorithms and/or new implementing architectures. The discussion will be centered on a developed methodology for high-level synthesis of data conversion systems both linear and non-linear, and how the presented methodology might be expanded to synthesize other analogue structures.

Synthesis of systems specified as interacting VHDL processes

This paper presents an approach to synthesis of hardware systems specified as interacting VHDL processes. Different from traditional high-level synthesis methodologies our approach takes into account the interactions and interdependence between concurrent processes. Two methods have been developed. The first method supports an unrestricted use of signals and wait statements and synthesizes synchronous hardware with global control of process synchronization for signal update. The second method allows hardware synthesis without the strict synchronization required by the VHDL simulation-based semantics. In both methods VHDL system specification are first translated into an internal design representation based on time Petri nets, which is then synthesized into hardware implementation structures at register-transfer level. Our main objective is to preserve simulation/synthesis correspondence during synthesis and to produce hardware that operates with a high degree of parallelism. Experimental results with practical design examples demonstrate that the proposed methods are efficient in terms of both resulted hardware and optimization time.

High-level DSP synthesis using concurrent transformations, scheduling, and allocation

This paper addresses high-level synthesis methodologies for dedicated digital signal processing (DSP) architectures used in the iterative Loop-based Minnesota Architecture Synthesis (MARS) design system. We present a novel concurrent scheduling and resource allocation algorithm which exploits inter-iteration and intra-iteration precedence constraints. The novel algorithm implicitly performs algorithmic transformations, such as pipelining and retiming, on the data-flow graphs during the scheduling process to produce solutions which are as good as those previously published and which executes in less time. MARS is capable of producing optimal and near-optimal schedules in fractions of seconds. Previous synthesis systems have focused on DSP algorithms which have single or lumped delays in the recursive loops. In contrast, MARS is capable of generating valid architectures for algorithms which have randomly distributed delays. MARS exploits these delays to produce more efficient architectures and allows our system to be more general. We are able to synthesize architectures which meet the iteration bound of any algorithm by unfolding, retiming, and pipelining the original data-flow graph.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

A quantitative methodology for rapid prototyping and high-level synthesis of signal processing algorithms

The paper introduces a systematic quantitative methodology to prototype deterministic recursive DSP algorithms onto multiple programmable signal processors. A scheduling framework that is based upon linear integer programming techniques is used to obtain rate, processor, delay, and communications optimal schedules for a given data flow graph representation of a signal processing algorithm. This powerful design synthesis environment facilitates optimal scheduling for randomly connected heterogeneous systems with multiple pipelined functional units and finite resources in VLSI. This framework can also be used in the high-level synthesis of efficient register-transfer level (RTL) VLSI descriptions from behavioral specifications. >

Operations research in the high-level synthesis of integrated circuits

The acceptance of high-level synthesis tools and methodologies by the design engineers depends on their efficiency in producing circuits with small silicon areas and high operating speeds. This paper shows how this efficiency can be achieved through the use of several operations research techniques applied to the many optimization problems that must be solved. These include: shortest path algorithms, integer programming techniques applied to silicon area minimization, force directed scheduling to optimize the number of operators and cost/speed trade-offs of logical gates. This paper presents several examples providing an operations research solution to each of them.