High-level Synthesis Design Research Articles

A High-level Synthesis Design Flow from ESL to RTL with Multi-parametric Optimization Objective

High-level synthesis (HLS) has emerged as the most sophisticated way to bridge the gap between electronic system level (ESL) and its respective structural building block at the register transfer level (RTL). As the growth of system complexity rapidly increases, the gap between high level and RTL needs to be filled. Much advancement has been made in the area of HLS, but none of the works have focused on a formal design methodology that bridges the gap from ESL to RTL considering multi-parametric optimization requirements. This paper exclusively focuses on the formal steps required for multi-parametric optimized HLS design flow. This is significant for industrial projects as well as for the development of fully automated HLS tools for the current generation of portable devices and high-end applications. The design flow initiates with the mathematical model of the application, performs multi-objective design space exploration and finally shows all the steps necessary after exploration for the HLS design. This paper explicitly focuses on highlighting the design flow with optimization of three parameters area, execution time and power consumption during HLS design while working under the prerequisite of stringent operational constraints. The implementation of the proposed method on Field-programmable Gate Array and the chip layout generation will also be presented.

FPGA Implementation of an Adaptive Filter Robust to Impulsive Noise: Two Approaches

Adaptive filters are used in a wide range of applications such as echo cancellation, noise cancellation, system identification, and prediction. Its hardware implementation becomes essential in many cases where real-time execution is needed. However, impulsive noise affects the proper operation of the filter and the adaptation process. This noise is one of the most damaging types of signal distortion, not always considered when implementing algorithms, particularly in specific hardware platforms. Field-programmable gate arrays (FPGAs) are used widely for real-time applications where timing requirements are strict. Nowadays, two main design processes can be followed for embedded system design, namely, a hardware description language (e.g., VHDL) and a high-level synthesis design tool. This paper proposes the FPGA implementation of an adaptive algorithm that is robust to impulsive noise using these two approaches. Final comparison results are provided in order to test accuracy, performance, and logic occupation.

Model-based design approach for embedded digital controllers design

Modern embedded systems are rapidly becoming a driving factor of the explosive growth of e-industry due to their increasingly sophisticated functionalities and complex features. At the same time, the advances of microelectronics and semiconductor technologies have enabled to increase the capacity-level integration of digital circuits like field programmable gate array (FPGA). The design of their systems is based on the challenge of increasing their performance by an abstraction of their implementation details to manage complexity. Designers need a more direct path between the specification and implementation. Different approaches to high-level synthesis design methodologies are currently used for high description language code generation. This paper examining a case study of the model-based design (MBD) approach using Xilinx System Generator, validated on two control drive applications such as direct current motor and alternative current motor. Results indicate that MBD approach enables designers to implement advanced algorithm including complex computing with good data precision and limited FPGA resources.

A high level synthesis design flow with a novel approach for efficient design space exploration in case of multi-parametric optimization objective

This paper introduces a novel approach to rapid Design Space Exploration (DSE) and presents a formalized High Level Synthesis (HLS) design flow with multi-parametric optimization objective using the same design space exploration approach. The proposed approach resolves issues related to DSE such as the precision of evaluation, time exhausted during evaluation and also automation of the exploration process. During DSE a conflicting situation always exists for the designer to concurrently maximize the accuracy of the exploration process and minimize the time spent during DSE analysis. This technique is capable of drastically reducing the number of architectural variants to be analyzed for accurate selection of the optimal design point in a short time. Unlike other proposed DSE approaches, the focus here is on determining the Priority Factor (PF) of the resources for final organization of the design space in increasing or decreasing order without requiring graphs or hierarchical tree arrangements to analyze the candidate variants. The proposed approach is capable of simultaneously optimizing many performance parameters viz. time of execution, power consumption, hardware area and cost. The DSE results for many benchmarks are presented along with a comparison with an existing DSE approach that uses the hierarchal structure method for architecture evaluation. Results indicated significant improvement in speedup compared to the existing approach.

Formal verification of high-level data-flow synthesis designs using relational modeling and symbolic computation

This paper presents a formal verification methodology of high-level data-flow synthesis process. Typically, given a data-flow description, the high-level data-flow synthesis tools perform high-level restructuring and data-flow transformations to produce an optimized architectural implementation. How to verify the correctness of the synthesis results is a key issue within the high-level data-flow synthesis process. Our approach adopts the relational modeling techniques from Kleene algebra with tests (KAT) and the symbolic computation methods from polynomial algebra to solve this verification problem. In this paper, we show how to extract target properties from the data-flow description by using KAT and how to construct the polynomial representation for the architectural implementation. Further, we demonstrate how a symbolic computation-based decision procedure is integrated into our framework to perform verification in a generalized bounded model checking (BMC) style. The experimental results on some public benchmark and practical designs demonstrate the efficiency of our approach and its applicability to large data-flow designs.

Hardware Implementation of a Robust Adaptive Filter: Two Approaches based in High-Level Synthesis Design Tools

Adaptive filters are used in a wide range of applications. Impulsive noise affects the proper operation of the filter and the adaptation process. This noise is one of the most damaging types of signal distortion, not always considered when implementing algorithms. Field Programmable Gate Array (FPGA) are widely used for applications where timing requirements are strict. Nowadays, two main design processes can be followed, namely, Hardware Description Language (HDL) and a High Level Synthesis (HLS) design tool for embedded system design. This paper describes the FPGA implementation of an adaptive filter robust to impulsive noise using two approaches based in HLS and the implementation has been carried out on the Xilinx ISE development system for FPGA prototyping. In order to test the system for functionality and implementation results, a widely used standard system identification problem is implemented. Results are provided in order to test accuracy, performance and logic occupation.

New design methodology with efficient prediction of quality metrics for logic level design towards dynamic reconfigurable logic

The importance of efficient area and timing estimation is well established in high level synthesis (HLS) since it allows more efficient exploration of the design space while providing HLS tools with the capability of predicting the effects of technology specific tools on the design space. Much of the previous work has focused on estimation techniques that use very simple cost models based solely on functional units (FUs). Those models are not accurate enough to allow effective design space exploration since the effects of interconnects can indeed dominate the final design cost. The situation becomes even worst when the design is targeted to dynamically reconfigurable logic (DRL) technologies since the multiplexer delay may contribute heavily on the overall delay. In addition, large number of configurable logic blocks could be used for communication rather than for implementing FUs. In this paper we Present a new HLS design flow, which performs an accurate estimation on area and timing for DRL circuits. It takes into account not only FUs area and delay, but also the interconnection and communication effects. We select our DRL LSI circuit [M. Meribout, M. Motomura, Method for compiling high level programs into hardware, Japanese Patent: JSP2000-313818, 2000; M. Motomura et al., An embedded DRAM-FPGA chip with instantaneous logic reconfiguration, in: Symposium on VLSI Circuits, July 1997, pp. 55-56] as our main concentration. We tested our method with several benchmarks and the results show that we receive good performance of the design, with area and timing estimated efficiently.

A method for area estimation of data-path in high level synthesis

This paper describes a new method to estimate the area of data paths generated during a High Level Synthesis (HLS) process, when the information concerning the circuit is not yet complete. Our method is more accurate and considers more factors than those used by other HLS systems of which we are aware. Our main concern is the interconnection area, often neglected by HLS systems, which has a strong influence on the final circuit area being optimized, as well as a high dependency on the technology used and on the circuit area itself. Predicting the area of a design layout with accuracy is important because it allows one to foresee whether the design will satisfy the area constraints, and will lend the allocator towards the best design among several possibilities with guarantees. Our estimations of the final standard-cell layout area are similar, or even more accurate, than those obtained following methods used by low-level design systems, which have much more information available. Due to the performance penalty their relatively high complexity will produce, these methods are unusable in an HLS system exploring a wide design space. Our estimation, on the contrary, has a low complexity and can be repeated time and again as the HLS design space is searched.