High-level Decision Diagrams Research Articles

On-Line Testing of digital VLSI circuits at Register Transfer Level using High Level Decision Diagrams

Nowadays On-Line Testing (OLT) has became one the essential technique to detect faults in digital VLSI circuits which occur during their normal operation. However, most of the works on OLT reported in the literature are at the gate level and these techniques take reasonable computational time. The major reason being these schemes work at bit level, leading to state explosion problem. This issue can be addressed by developing OLT schemes at higher description levels of the circuits. In this paper, we present an OLT scheme at Register Transfer Level (RTL) description using High Level Decision Diagrams (HLDDs) and design corresponding on-line tester circuits. Experiments on different HLSynth92 benchmark circuits show that the test generation time is greatly improved using HLDDs, thus, large circuits can be easily handled. Further, it achieves lower area overhead at similar fault coverage compared to OLT schemes at gate level.

Генерация тестов для цифровой аппаратуры на основе высокоуровневых моделей

Hardware testing is a process aimed at detecting manufacturing faults in integrated circuits. To measure test quality, two main metrics are in use: fault detection abilities (fault coverage) and test application time (test length). Many algorithms have been suggested for test generation; however, no scalable solution exists. In this paper, we analyze applicability of functional tests generated from high-level models for low-level manufacturing testing. A particular test generation method is considered. The input information is an HDL description. The key steps of the method are system model construction and coverage model construction. Both models are automatically extracted from the given description. The system model is a representation of the design in the form of high-level decision diagrams. The coverage model is a set of LTL formulae defining reachability conditions for the transitions of the extended finite state machine. The models are translated into the input format of a model checker. For each coverage model formula the model checker generates a counterexample, i.e. an execution that violates the formula (makes the corresponding transition to fire). The approach is intended for covering of all possible execution paths of the input HDL description and detecting dead code. Experimental comparison with the existing analogues has shown that it produces shorter tests, but they achieve lower stuck-at fault coverage comparing with the dedicated approach. An improvement has been proposed to overcome the issue.

Генерация функциональных тестов для HDL-описаний на основе проверки моделей

Automated test generation is a promising direction in hardware verification research area. Functional test generation methods based on models are widespread at the moment. In this paper, a functional test generation method based on model checking is proposed and compared to existing solutions. Automated model extraction from the hardware design’s source code is used. Supported HDLs include VHDL and Verilog. Several kinds of models are used at different steps of the test generation method: guarded action decision diagram (GADD), high-level decision diagram (HLDD) and extended finite-state machine (EFSM). The high-level decision diagram model (which is extracted from the GADD model) is used as a functional model. The extended finite-state machine model is used as a coverage model. The aim of test generation is to cover all the transitions of the extended finite state machine model. Such criterion leads to the high HDL source code coverage. Specifications based on transition and state constraints of the EFSM are extracted for this purpose. Later, the functional model and the specifications are automatically translated into the input format of the nuXmv model checking tool. nuXmv performs model checking and generates counterexamples. These counterexamples are translated to functional tests that can be simulated by the HDL simulator. The proposed method has been implemented as a part of the HDL Retrascope framework. Experiments show that the method can generate shorter tests than the FATE and RETGA methods providing the same or better source code coverage.

Software-based self-test generation for microprocessors with high-level decision diagrams

Software-based self-test generation for microprocessors with high-level decision diagrams

Automated design error debug using high-level decision diagrams and mutation operators

The paper proposes a method for locating design errors at the source-level of Register-Transfer Level (RTL) hardware description language code using the design representation of High-Level Decision Diagram (HLDD) models and correcting them by applying mutation operators. The error localization is based on backtracing the mismatched and matched outputs of the design under verification on HLDDs. As a result of the localization step, all the variables in the RTL description receive a suspiciousness score. Subsequently, a mutation-based correction algorithm is applied providing automated correction for the design under verification. Experiments on a set of sequential RTL benchmarks show that the method is capable of locating the design errors injected with a high accuracy and a short run time. In fact a majority of the errors injected in the experiments were identified as top suspects by the proposed diagnosis algorithm. Furthermore, we show that because of this localization accuracy the mutation-based correction requires very small number of iterations and thus a short run-time.

Overview about low-level and high-level decision diagrams for diagnostic modeling of digital systems

BDDs have become the state-of-the-art data structure in VLSI CAD. In this paper, a special class of BDDs is presented called Structurally Synthesized BDDs (SSBDD). The idea of SSBDDs is to establish one-to-one mapping between the nodes of SSBDDs and signal paths in the related digital circuit. Such a mapping allowed to investigate and solve with SSBDDs a lot of test and diagnosis related problems of digital circuits, which are associated explicitly with the structure. Such problems are, for example, direct representation of faults, fault collapsing and fault masking, delay testing, hazard detection, etc. The main concept of using SSBDDs is laying on the topological view on the graphs, where each path on a SSBDD can be mapped directly to a subcircuit of the related circuit. Such a topological view allowed to generalize the knowledge and methods of test synthesis and fault analysis from the Boolean level to higher register-transfer and behavior levels of digital systems by introducing High-Level DDs (HLDD). The paper gives a short historical overview of the development of SSBDDs and HLDDs.

Canonical representations of high-level decision diagrams

In this paper we give a short overview of the decision diagrams, and define a special class of high-level decision diagrams (HLDD) for formal representation of digital systems. We show how the HLDDs can be used for high-level verification of digital systems. For this purpose, HLDDs are represented by characteristic polynomials as a canonical form of HLDDs. The polynomials can be used for proving the equivalence between two HLDDs, which have the same functionalities but may have different internal structures. Some possibilities are shown how to cope with the complexity of the verification problem.

Application of high-level decision diagrams for simulation-based verification tasks

This paper describes the advantages of the application of a system representation model, called High-Level Decision Diagrams (HLDDs), for hardware functional verification. Two tasks of simulation-based verification, considered in this paper, are assertion checking and code coverage analysis. Assertion checking employs temporal extension of an existing HLDD model aimed at supporting temporal properties, expressed in Property Specification Language (PSL). The described approach to code coverage analysis provides for more accurate results than traditional VHDL code coverage methods. Experimental results show the feasibility and efficiency of the HLDDs- based approaches.

PSL Assertion Checking Using Temporally Extended High-Level Decision Diagrams

This paper proposes a novel method for the simulation-based checking of assertions written in the PSL language. The method uses a system representation model called High-Level Decision Diagrams (HLDDs). Previous works have shown that HLDDs are an efficient model for simulation and convenient for diagnosis and debug. The presented approach proposes a temporal extension for the existing HLDD model aimed at supporting temporal properties expressed in Property Specification Language (PSL). Other contributions of the paper are a methodology for direct conversion of PSL properties to HLDD and modification of the HLDD-based simulator for assertion checking support. Experimental results show the feasibility and efficiency of the proposed approach.

Mixed hierarchical-functional fault models for targeting sequential cores

Current work presents a set of fault models allowing high coverage for sequential cores in systems-on-a-chip. We propose a novel approach combining a hierarchical fault model for functional blocks, a functional fault model for multiplexers and a mixed hierarchical-functional fault model for comparison operators, respectively. The fault models are integrated into a fast high-level decision diagram based test path activation tool. According to the experiments, the proposed method significantly outperforms state-of-the-art test pattern generation tools. The main new contribution of this paper is a formal definition of high-level decision diagram representations and the combination of the three fault models in order to target high gate-level stuck-at fault coverage for sequential cores.