Automated design error debug using high-level decision diagrams and mutation operators

Abstract

The paper proposes a method for locating design errors at the source-level of Register-Transfer Level (RTL) hardware description language code using the design representation of High-Level Decision Diagram (HLDD) models and correcting them by applying mutation operators. The error localization is based on backtracing the mismatched and matched outputs of the design under verification on HLDDs. As a result of the localization step, all the variables in the RTL description receive a suspiciousness score. Subsequently, a mutation-based correction algorithm is applied providing automated correction for the design under verification. Experiments on a set of sequential RTL benchmarks show that the method is capable of locating the design errors injected with a high accuracy and a short run time. In fact a majority of the errors injected in the experiments were identified as top suspects by the proposed diagnosis algorithm. Furthermore, we show that because of this localization accuracy the mutation-based correction requires very small number of iterations and thus a short run-time.