On-Line Testing of digital VLSI circuits at Register Transfer Level using High Level Decision Diagrams

Abstract

Nowadays On-Line Testing (OLT) has became one the essential technique to detect faults in digital VLSI circuits which occur during their normal operation. However, most of the works on OLT reported in the literature are at the gate level and these techniques take reasonable computational time. The major reason being these schemes work at bit level, leading to state explosion problem. This issue can be addressed by developing OLT schemes at higher description levels of the circuits. In this paper, we present an OLT scheme at Register Transfer Level (RTL) description using High Level Decision Diagrams (HLDDs) and design corresponding on-line tester circuits. Experiments on different HLSynth92 benchmark circuits show that the test generation time is greatly improved using HLDDs, thus, large circuits can be easily handled. Further, it achieves lower area overhead at similar fault coverage compared to OLT schemes at gate level.