Test Calculation for Logic and Delay Faults in Digital Circuits

Abstract

The paper presents a test calculation principle which serves for producing tests for logic and delay faults in digital circuits. Switch-level logic faults in CMOS circuits are also considered. The delay faults manifest themselves in the incorrect timing behavior of some logic elements within the network. Both single and multiple faults are included. The proposed method handles multi-valued logic, where the number of logic values is unlimited. The level of circuit modeling is also allowed to vary in a wide range: switch level, gate level, functional level, register-transfer level are equally allowed. Both combinational and sequential circuits are considered. The principle is comparatively simple, and it yields an opportunity to be realized by an efficient computer program.