High-level Converter Research Articles

Review and Case Study on Control of Induction Motor Using High-Level Converter

Review and Case Study on Control of Induction Motor Using High-Level Converter

Common-Mode Voltage Elimination of Multilevel Converters With Reduced Switching Loss Using Sawtooth-Carrier-Based PWM

This paper proposes an asymmetrical switching pattern to eliminate common-mode voltage (CMV) in multilevel converters while reducing switching loss by rearranging the switching sequence to minimize the number of level-shifts. In contrast to the existing symmetrical switching pattern, this approach achieves CMV elimination without increasing switching loss. To implement this asymmetrical switching pattern, a simple sawtooth carrier-based PWM scheme is proposed that avoids the need for complicated space vector modulation (SVM) computation, particularly for high-level converters. The proposed method's effectiveness is demonstrated through simulations and experimental results for the three-phase cascaded H-bridge converter and boost seven-level active neutral-point-clamped converter.

Matrix-Based Approach for Open-Circuit Fault-Tolerant Analysis and PWM Design of Active Neutral-Point-Clamped Converters

Active neutral-point-clamped converter adds open-circuit fault-tolerant (OCFT) capability compared with the widely used original neutral-point-clamped (NPC) topology. However, such capability is hard to utilize due to difficulties in pulse-width modulation (PWM) design and the randomness of failure points, particularly in high-level converters. Current research mainly focused on low-level topologies with a limited number of fault scenarios; moreover, the analysis and design are performed in a nonsystematic way. In this article, the OCFT operations of active NPC (ANPC) converters with multiple fault switches are investigated and the systematic PWM design process is proposed. First, different matrices are proposed for the ANPC converters to capture the complicated topology information and achieve an exhaustive analysis of the topological redundancy. Then, a step-by-step process is proposed to derive the suitable OCFT PWM patterns. The five-level ANPC converter is investigated as an example. Its experimental results validate that the proposed approach can 1) properly predict the behavior of converters systematically so that the tolerable faults and intolerable can be identified during the design procedure, and 2) the inherent fault-tolerant capability of the five-level ANPC converter can be guaranteed through the proposed method, and 3) multiswitch open-circuit faults can be easily dealt with by implementing suitable carrier-based PWM schemes.

Integrated Framework for Development, Emulation, and Testing of High-Level Converter Control Functions for Distributed Generation Sources

With the increase in power installed from distributed generation sources (DGS), many problems have appeared following the utilisation of novel topologies and structures. Higher-level controllers for the safe operation of power grids with a high penetration of DGS must be developed. This task becomes difficult as the size and complexity of modern power systems have increased. The development and testing of these systems under strict human supervision controlling each step of the testing procedure is no longer viable. This paper presents a comprehensive integrated platform based on an HIL emulator for the development and testing of electric power systems rich in DGS. Essentially, DGS is considered a controllable black-box system. A detailed calculation of the power references for an arbitrary DGS is shown. The paper also describes the utilisation of enhanced Python scripting which was designed to load all network-related data, start the emulation, collect the data, and generate reports. Furthermore, fully developed controller built-in oscilloscope functionality is introduced. The incorporated oscilloscope facilitates non-intrusive DGS controller data acquisition and analysis, reducing the need for external measurements. The proposed framework was verified by a case study in which a grid topology consisting of 26 nodes was emulated on parallel CHIL infrastructure. Four active and twenty-two passive nodes were instantiated and their reaction to a distribution network grid faults was examined. DGS converter control was executed in external controllers outside of the dedicated HIL environment. All DGSs were governed by different control strategies, regarding maximisation of active/reactive power production, minimisation of the active/reactive power oscillations, adjustable positive/negative components ratio, or without any limitations under voltage disturbances. Real-time experiments confirmed the usefulness and flexibility of the proposed framework concept.

Phase-Disposition PWM Based 2DoF-Interleaving Scheme for Minimizing High Frequency ZSCC in Modular Parallel Three-Level Converters

This paper proposes a two-degree-of-freedom (2DoF) interleaving scheme based on phase-disposition (PD) PWM for minimizing the high-frequency zero-sequence circulating current (ZSCC) in modular interleaved three-level converters. The method incorporates an internal interleaving by phase-shifting the carriers in each individual converter, and an external interleaving by phase-shifting the carriers of the different converters. A general harmonic distribution analysis which is valid for all types of voltage source converters is carried out to simplify the evaluation of the proposed method. A comprehensive evaluation of the proposed method shows that the PD-2DoF interleaving scheme produces the lowest ZSCC maximum value as compared to existing approaches. Moreover, it can achieve comparable performances as existing methods do in terms of output quality and common mode voltage magnitude, showing a great potential for practical implementation. Simulation and experimental results are obtained to demonstrate the performance of the proposed method. Generalization of the 2DoF interleaving scheme to high-level converter is also discussed in this paper.

Carrier-Based Stair Edge PWM (SEPWM) for Capacitor Balancing in Multilevel Converters With Floating Capacitors

Multilevel converters with floating capacitors (FCs) are widely applied in recent years in a wide range of industrial applications from high-voltage direct current systems to high power drives. However, some FC topologies lack complete FC voltage balancing capability due to the inherent topology limitation or the insufficient switching state for capacitor balancing. This will result in large ripples on capacitors at low frequency (such as fundamental frequency), limiting their performance and application, particularly, when the fundamental frequency is very low in low-speed drive operations. Typical examples of those multilevel converters are modular multilevel converters (MMC), nested neutral-point-clamped (NNPC) converter, etc. In order to improve the FC balancing for this kind of multilevel converters, this paper proposes a carrier-based pulse-width modulation (PWM) method, named stair edge PWM method. This method can obtain sufficient redundant switching states for FC voltage balancing by producing multiple levels in one PWM period. The FC voltage balancing is thus achieved at switching frequency, which can greatly reduce the capacitor voltage ripple and therefore enable the use of much smaller FCs. Meanwhile, the voltage stress on each device and low $dv/dt$ feature are still the same as the normal multilevel operation, reserving two of the most salient features of multilevel converters. The proposed method also features much simpler and easier implementation compared with space-vector-based approaches, particularly when high-level converters are considered. An application example using a four-level NNPC converter is provided in this paper. The effectiveness and performance of the proposed method are verified by both simulation and experiment.

Transistor-Level Synthesis of Pipeline Analog-to-Digital Converters Using a Design-Space Reduction Algorithm

A novel transistor-level synthesis procedure for pipeline ADCs is presented. This procedure is able to directly map high-level converter specifications onto transistor sizes and biasing conditions. It is based on the combination of behavioral models for performance evaluation, optimization routines to minimize the power and area consumption of the circuit solution, and an algorithm to efficiently constraint the converter design space. This algorithm precludes the cost of lengthy bottom-up verifications and speeds up the synthesis task. The approach is herein demonstrated via the design of a 0.13 μm CMOS 10 bits@60 MS/s pipeline ADC with energy consumption per conversion of only 0.54 pJ@1 MHz, making it one of the most energy-efficient 10-bit video-rate pipeline ADCs reported to date. The computational cost of this design is of only 25 min of CPU time, and includes the evaluation of 13 different pipeline architectures potentially feasible for the targeted specifications. The optimum design derived from the synthesis procedure has been fine tuned to support PVT variations, laid out together with other auxiliary blocks, and fabricated. The experimental results show a power consumption of 23 mW@1.2 V and an effective resolution of 9.47-bit@1 MHz. Bearing in mind that no specific power reduction strategy has been applied; the mentioned results confirm the reliability of the proposed approach.