High K Research Articles

Comprehensive analysis of determining factors of the effective work function of TiAlC/TiN metal gates for advanced gate-all-around CMOS integration

Abstract We have examined the determining factor of the effective work function (EWF) for an n-channel MOSFET (n-type EWF) in TiAlC/TiN metal gates on high-k gate dielectrics (HK). From electrical and physical evaluations of the bottom TiN between HK and TiAlC (BTM-TiN), the obtained results suggest that the dominant factor for the n-type EWF of TiAlC/TiN metal gates is not the fixed charge in the gate dielectric but the vacuum work function of BTM-TiN. It was found that TiN with low oxygen content has a vacuum work function of 3.8 eV, suitable for an n-channel MOSFET although TiN has been believed to be suitable for a p-channel MOSFET. We also found that its vacuum work function increases with increasing oxygen content. Based on these results, we proposed an oxygen scavenging from BTM-TiN(O) by Al in TiAlC as a novel mechanism for the n-type EWF for TiAlC/TiN metal gates.

High-performance van der Waals stacked transistors based on ultrathin GaPS4 dielectrics.

Exploring high-κ gate dielectrics is crucial for the achievement of high-performance field-effect transistors (FETs). Here, we report the synthesis of a few-layer wide bandgap semiconductor gallium thiophosphate (GaPS4), which can be easily mechanically exfoliated from a bulk material. The few-layered GaPS4 flakes exhibit a relative dielectric constant of approximately 5.3. Two-dimensional (2D) van der Waals heterostructure FETs utilizing atomically smooth GaPS4 flakes as the top-gate dielectric layer and MoS2 as the channel material were fabricated, showing a high on-off ratio exceeding 107 with a subthreshold swing as low as 80 mV per decade. Our findings indicate that few-layer GaPS4 is a high-performance dielectric candidate for two-dimensional transistors, which enrich the high-κ 2D community and pave the way for fabricating modern electronic devices.

UV/Ozone-Induced Interface Engineering for High-Performance Horizontal Organic Light-Emitting Transistors Operating at Low Voltage.

Multifunctional organic light-emitting transistors (OLETs), which combine electric-switching and light-producing capabilities into a single device, are attracting increasing interest as promising candidates for new-generation display technology. Despite advancements in the design of organic luminescent materials and the optimization of device geometry configurations, maintaining operating voltage low while enhancing optical performances remains a key challenge in horizontally structured OLETs. Here, a simple and effective interfacial engineering strategy is employed to improve the optical properties of horizontal OLETs operating at low voltage, by introducing ultraviolet ozone (UVO)-induced surface modification on high-k dielectrics. It takes the role to not only control the surface activation states of dielectric layers but also optimize the growth dynamics behavior of channel film benefitting from the strong interfacial interaction between chemically modified dielectric surface and channel seed molecules. The optimized horizontal-channel OLET exhibits a significantly high brightness of 9,484 cdm- 2, more than 25 times greater than that of untreated OLETs (347 cdm- 2), along with a peak EQE of 9.64%, a low operating voltage of 15 V, and good dynamic gate stress stability, outperforming other reported horizontal-channel high-performance OLETs. This work demonstrates that dielectric/semiconductor interface engineering is essential for high-performance transistor-based optoelectronic devices including horizontal OLETs.

Impact of high-k insulators on electrical properties of junctionless double gate strained transistor

High-k dielectric insulators are required to reduce leakage and increase transistor performance. They are able to impact the mobility of carriers in transistors positively, leading to better device performance in advanced transistor architecture. Nevertheless, an in-depth analysis of how high-k dielectric insulators influence transistor characteristics must be carried out to determine their suitability. The objective of this study is to investigate the impact of high-k insulators towards electrical properties of junctionless double gate strained transistor. The simulation works is done using process/device simulator Silvaco Athena/Atlas. Based on the retrieved results, the magnitude of I<sub>ON</sub>, on-off ratio, g<sub>m</sub>, and C<sub>int</sub> for TiO<sub>2</sub>-based device are approximately 63%, 99%, 62%, and 89% respectively higher than the lowest permittivity material-based device. The TiO<sub>2</sub>-based device also exhibits the lowest magnitude in I<sub>OFF</sub> and SS compared to others. However, a significant degradation in f<sub>T</sub> magnitude have been observed for TiO<sub>2</sub>-based device significantly due to its large capacitances

Application of Solution-Processed High-Entropy Metal Oxide Dielectric Layers with High Dielectric Constant and Wide Bandgap in Thin-Film Transistors.

High-k metal oxides are gradually replacing the traditional SiO2 dielectric layer in the new generation of electronic devices. In this paper, we report the production of five-element high entropy metal oxides (HEMOs) dielectric films by solution method and analyzed the role of each metal oxide in the system by characterizing the film properties. On this basis, we found optimal combination of (AlGaTiYZr)Ox with the best dielectric properties, exhibiting a low leakage current of 1.2 × 10-8 A/cm2 @1 MV/cm and a high dielectric constant, while the film's visible transmittance is more than 90%. Based on the results of factor analysis, we increased the dielectric constant up to 52.74 by increasing the proportion of TiO2 in the HEMOs and maintained a large optical bandgap (>5 eV). We prepared thin film transistors (TFTs) based on an (AlGaTiYZr)Ox dielectric layer and an InGaZnOx (IGZO) active layer, and the devices exhibit a mobility of 18.2 cm2/Vs, a threshold voltage (Vth) of -0.203 V, and an subthreshold swing (SS) of 0.288 V/dec, along with a minimal hysteresis, which suggests a good prospect of applying HEMOs to TFTs. It can be seen that the HEMOs dielectric films prepared based on the solution method can combine the advantages of various high-k dielectrics to obtain better film properties. Moreover, HEMOs dielectric films have the advantages of simple processing, low-temperature preparation, and low cost, which are expected to be widely used as dielectric layers in new flexible, transparent, and high-performance electronic devices in the future.

(Invited) Applications of Oxygen Inserted Epitaxy

Silicon remains the semiconductor material of choice for most electronic applications of semiconductors and the silicon–silicon dioxide interface is one of the most studied interfaces. Over the past decade or more, epitaxial silicon-germanium (eSiGe) has found increasing applications in advanced logic, first for PMOS compressive source-drain (S/D) stressors, then as a channel material in high-k metal gate (HKMG) devices to help control the PMOS Vt, and more recently as a sacrificial layer to enable stacked nanosheets and even as a S/D liner to reduce phosphorus diffusion into the undoped nanosheets. Oxygen inserted (OI) silicon epitaxy was originally developed to complement and bridge the gap between silicon and silicon-germanium, and it has found applications ranging from improved figure of merit power devices to the most advanced nanosheet applications. In this paper we will provide an overview of OI silicon devices, their fundamental characterization and the electrical and physical benefits offered for a variety of semiconductor applications. Introduction Oxygen-inserted (OI) silicon had an unusual genesis for a semiconductor material, in that it was first explored using ab-initio quantum mechanical simulation. It was found that by carefully inserting a partial monolayer of oxygen during silicon epitaxy a stable layer could be manufactured where the individual oxygen atoms arranged themselves on a silicon-silicon bond, but that overall, the silicon retained its regular lattice, and the silicon-oxygen coordination was only one, as opposed to four in regular silicon dioxide. The idealized lattice configuration is shown in Fig. 1 (a). This configuration is technically thermodynamically metastable, but with a significant energetic barrier to formation of four-fold coordinated silicon dioxide, so that it can survive conventional semiconductor processing. Whereas a single oxygen atom is known to rapidly diffuse in silicon, there is a thermodynamic self-stabilization when the oxygen concentration has an aerial density of the order of 1E15cm-2, with an upper limit dependent both on the specific epitaxial recipe and the required defect density. If all available silicon bonds have attached oxygen, it is difficult to maintain high quality epitaxy. On the other hand, OI silicon has passed the most rigorous defect density requirements for advanced logic applications. Dopant engineering - simulation Oxygen is highly electronegative, and ab initio simulation shows that there is charge transfer in the silicon lattice in the near vicinity of the inserted oxygen as shown in Fig 1 (b). This leads to a change in the formation enthalpy for a single substitutional dopant atom or addition of a silicon point defect, vacancy or interstitial as shown in Fig 1 (c). The figure indicates that substitutional boron and phosphorus will have an energetic preference to be two or three silicon lattice atoms away from the inserted oxygen, whereas silicon point defects prefer to be coincident with the oxygen. As a result, the OI layers disrupt the diffusion of dopant-interstitial pairs, substantially reducing the dopant diffusion. Dopant engineering – experimental data OI silicon has been proven to create unique abrupt doping profiles for a variety of silicon and silicon germanium devices. In power devices, reducing the vertical and lateral diffusion below the OI silicon layer can be used to engineer significant improvement in critical figures of merit, such as the tradeoff between specific ON resistance (Rsp) and the breakdown voltage, and improved time constant (Ron∙ Coff) and reduced body current in RF power devices, while maintaining breakdown voltage. In advanced 3D applications, a 2nm thin liner of OI silicon has proven effective to create a diffusion barrier between highly doped epitaxial source/drain regions and undoped channels. By reducing dopant up-diffusion, thermally robust super-steep retrograde profiles can be created, which can be used to reduce local threshold voltage mismatch in both NMOS and PMOS devices by more than 50%. In gate-first HKMG planar CMOS applications, SiGe channel is used in the PMOS to facilitate Vt engineering. A thin OI silicon layer below the SiGe channel can be used to maintain a super-steep retrograde channel profile after HKMG formation and subsequent thermal processing. Interface interactions It has recently been discovered that OI silicon can also be used to engineer adjacent interfaces. For example, it has been shown by cryogenic measurements that OI silicon reduces surface roughness scattering of the silicon-dielectric interface. Also, OI silicon can reduce the interfacial dipole formed during HKMG processing, with benefits in reduced remote charge scattering and improved reliability.These and other examples of engineered silicon and silicon-germanium devices will be discussed in detail. Figure 1

All Solution-Processed High-Performance MoS2 Thin Film Transistors with the High-k Perovskite Oxide Dielectric

Solution-processable van der Waals (vdW) materials with atomic layered crystal structures, are increasingly recognized as promising components for emerging electronic device applications. These materials offer exceptional quality and stability, coupled with the advantage of large-scale and low-temperature processability. Among these, van der Waals-assembled thin films made from transition metal dichalcogenides in solution have recently emerged as highly potential candidates for fabricating high-performance thin-film transistors (TFTs). Despite recent progress, fully solution-processed vdW electronics remain elusive, primarily due to the absence of suitable dielectric materials and scalable fabrication methodologies. In this report, we introduce the all solution-processed MoS2 TFTs, incorporating perovskite oxides as high-k gate dielectrics. The fabrication process involves preparing colloidal inks for each constituent layer through chemical or electrochemical exfoliation methods, followed by sequential assembly processes forming the semiconductor/dielectric heterostructure. All fabrication steps are performed at temperatures below 250 ℃. The resulting MoS2 TFTs, utilizing Dion-Jacobson-phase perovskite as the dielectric layer, demonstrate superior device characteristics. Notably, they exhibit an ON/OFF ratio exceeding 106, including high mobility (>10 cm2 V-1s-1). Additionally, the integration of high-k dielectric materials enables the transistors to operate at low leakage current (~10-11 A) and very low voltages, around approximately 5 V, significantly reducing power consumption. These TFTs are also compatible with flexible substrates, which further demonstrates their robustness and adaptability in a variety of electronic applications. The successful demonstration of low-temperature fabrication techniques for high-performance MoS2 TFTs not only marks a significant advancement in the field of solution-processable electronic devices but also paves the way for cost-effective, scalable electronics that are capable of hetero-integration.

Low-Temperature Ozone Atomic-Level Trimming on Ge Interfused Channel with Subthreshold Characterization Enhancement for Gate-All-Around Si Nsstransistors

Recently, stacked nanowire/nanosheet GAAFETs have been under intensive investigation owing to their excellent electrostatics and short-channel control, which can fulfill the requirement of the 5-nm technology node and beyond. However，GAAFETs are affected by the overall thermal budget of the integration process, and after channel release removes the SiGe stack, the presence of Ge residues on the Si channel surface increases the interfacial trap charge, leading to increased defects on the channel surface, which affects the subthreshold characteristics of the device and increases the SS. Due to the tendency to overcorrode during the channel release process and the effect of Ge diffusion, the NS surface roughness becomes larger, leading to enhanced surface scattering and resulting in a decrease in the effective mobility of the carriers, in which the surface roughness change mainly affects the surface roughness scattering and Coulomb scattering of the carriers. Conventional interface treatment methods cannot accomplish the reduction of SS and surface roughness at the same time, so in this paper, we propose a low-temperature ozone atomic-level stripping process method to thin the trench of the gate-all-around NS device. Removing Ge diffused into the trench due to the thermal budget, reducing the trench surface roughness and the surface state, and repairing the free Si and Ge bonds caused by the high thermal budget and the diffusion of Ge. Finally, the device subthreshold characteristics are optimized.In this paper, the verification is first carried out on capacitor wafers by using low temperature ozone atomic level stripping treatment on silicon wafers with simulated channel surfaces for 1/2/5 times, respectively. After O3 treatment, the interface state density is significantly reduced, the interface optimization results results are shown in Fig1. At the same time the above operation makes the thickness of the oxide layer reduce significantly, the EOT is reduced, resulting in a lower K value. So two O3 treatments are applied to the channel surface after channel release in the actual device. The result SS is reduced from 67.5 to 64.3 mV/dec for PFET and reduced from 67.8 to 64.8 mV/dec for NFET (Fig. 2), the device characteristics are significantly improved.N-type MOSCAPs were fabricated with the standard high-k/metal-gate (HK/MG) on a Si0.7Ge0.3 epitaxy layer on p-type bulk-Si (100) wafers. The process flows and key process-step techniques are shown. To reflect the channel interface issues of GAA NSFETs, the capacitors were fabricated on the epitaxy substrate with at a rapid thermal annealing (RTA) and a simulated channel release process. Firstly, 12 nm Si and 18 nm Si0.7Ge0.3 were epitaxially grown on the substrate as the channel surface, and an RTA of 850 ℃ for 75s was performed based on the general thermal budget requirement of the front-end process. Next, the SiGe layer was removed by channel release solution. Afterwards, the substrate was processed by O3 for 2 second after wet-etch SiGe 20s, and then rinsed in DHF for 20s to remove the oxidation. Figure 1

(Invited) Atomic-Scale Design of Advanced Transistors Via Ultrathin Negative Capacitance Gate Stacks

Negative capacitance [1,2] has emerged as a promising solution to overcome fundamental energy-efficiency limits in conventional electronics, in which internal ferroelectric order within the gate stack of a field-effect transistor can enable low-power operation. Thus far, claims of negative capacitance have been primarily demonstrated in perovskite-structure thick films or through misleading “S-curve” transient experiments in fluorite-structure thick films. However, integration into advanced semiconductor technology nodes will require stabilization at the ultrathin regime and evidence of capacitance enhancement (i.e. lower equivalent oxide thickness, EOT) to enable highly-scaled lower-power operation.Here, we present evidence of negative capacitance in atomic-scale HfO2-ZrO2 heterostructures down to two-nanometers and one-nanometer thickness [3,4], leveraging our recent work examining the atomic limits of fluorite-structure ferroelectricity on silicon [5,6]. ALD HfO2-ZrO2-based heterostructures on Si-SiO2 demonstrate ultralow EOT without having to scavenge the SiO2 interlayer, in stark contrast to conventional high-κ metal gate (HKMG) technology [7]. Accordingly, in comparison to industrial HKMG benchmarks, these SiO2-buffered antiferroelectric-ferroelectric gate stacks boast favorable performance and can provide multiple node technology boosts [8]. Due to seamless integration and transition from high-κ HfO2-based dielectrics to negative-κ HfO2-ZrO2-based ferroelectrics, these NC stacks have already been validated and integrated by prototyping foundries [8] and semiconductor foundries [9].In this talk, key differences between static versus transient negative capacitance will be highlighted to clarify misleading literature and explain their relative benefits for logic transistors [3,4] versus other applications [10]. Perspectives on further routes to EOT scaling via negative capacitance gate stacks for beyond-1-nm-node logic technology will also be discussed. R Landauer. “Can capacitance be negative.” Collect. Phenom. 2, 167–170 (1976).S Salahuddin & S Datta. “Can the subthreshold swing in a classical FET be lowered below 60 mV/decade?” in 2008 IEEE International Electron Devices Meeting (IEEE, 2008).S Cheema et al. “Ultrathin ferroic HfO2–ZrO2 superlattice gate stack for advanced transistors.” Nature 604, 65–71 (2022).S Cheema et al. “Physical and electric thickness limits of negative capacitance.” In preparation (2024).S Cheema et al. “Emergent ferroelectricity in subnanometer binary oxide films on silicon.” Science 376, 648–652 (2022).S Cheema et al.“Enhanced ferroelectricity in ultrathin films grown directly on silicon.” Nature 580, 478–482 (2020).T Ando “Ultimate Scaling of High-κ Gate Dielectrics: Higher-κ or Interfacial Layer Scavenging?” Materials 5, 478–500 (2012).N Shanker et al. “CMOS Demonstration of Negative Capacitance HfO2-ZrO2 Superlattice Gate Stack in a Self-Aligned, Replacement Gate Process.” in 2022 International Electron Devices Meeting (IEDM) 34.3.1-34.3.4 (IEEE, 2022).S Jo. et al. “Negative differential capacitance in ultrathin ferroelectric hafnia.” Nat. Electron. 6, 390–397 (2023).S Cheema et al.“Giant energy storage and power density negative capacitance superlattices.” Nature doi:10.1038/s41586-024-07365-5 (2024).

High-κ monocrystalline dielectrics for low-power two-dimensional electronics.

The downscaling of complementary metal-oxide-semiconductor technology has produced breakthroughs in electronics, but more extreme scaling has hit a wall of device performance degradation. One key challenge is the development of insulators with high dielectric constant, wide bandgap and high tunnel masses. Here, we show that two-dimensional monocrystalline gadolinium pentoxide, which is devised through combining particle swarm optimization algorithm and theoretical calculations and synthesized via van der Waals epitaxy, could exhibit a high dielectric constant of ~25.5 and a wide bandgap simultaneously. A desirable equivalent oxide thickness down to 1 nm with an ultralow leakage current of ~10-4 A cm-2 even at 5 MV cm-1 is achieved. The molybdenum disulfide transistors gated by gadolinium pentoxide exhibit high on/off ratios over 108 and near-Boltzmann-limit subthreshold swing at an operation voltage of 0.5 V. We also constructed inverter circuits with high gain and nanowatt power consumption. This reliable approach to integrating ultrathin monocrystalline insulators paves the way to future nanoelectronics.

Ultrafast reconfigurable direct charge trapping devices based on few-layer MoS2

Abstract Charge trapping devices incorporating 2D materials and high-κ dielectrics have emerged as promising candidates for compact, multifunctional memory devices compatible with silicon-based manufacturing processes. However, traditional charge trapping devices encounter bottlenecks including complex device structure and low operation speed. Here, we demonstrate an ultrafast reconfigurable direct charge trapping device utilizing only a 30 nm-thick Al2O3 trapping layer with a MoS2 channel, where charge traps reside within the Al2O3 bulk confirmed by transfer curves with different gate-voltage sweeping rates and photoluminescence (PL) spectra. The direct charging tapping device shows exceptional memory performance in both three-terminal and two-terminal operation modes characterized by ultrafast three-terminal operation speed (∼300 ns), an extremely low OFF current of 10−14 A, a high ON/OFF current ratio of up to 107, and stable retention and endurance properties. Furthermore, the device with a simple symmetrical structure exhibits V D polarity-dependent reverse rectification behavior in the high resistance state (HRS), with a rectification ratio of 105. Additionally, utilizing the synergistic modulation of the conductance of the MoS2 channel by V D and V G, it achieves gate-tunable reverse rectifier and ternary logic capabilities.

Device to circuit level implementation of JL-NSFET for DC/analog/RF applications at sub-5nm technology node: design optimization and temperature analysis

Abstract This manuscript introduces, for the first time, a novel approach that incorporates a comprehensive analysis of sheet variations (1–5) and every individual sheet wise temperature variation, and as well as an investigation of various GS high-k gate dielectrics in Junction-less (JL) Nanosheet FET (JL-NSFET). The study starting from device level (Digital/Analog/Radio Frequency) to circuit (CMOS Inverter and ring oscillator) as a whole package is investigated through well calibrated TCAD simulation and the results portrayed. NSFETs are the ultimate choice for integrated circuits (ICs) at sub-5 nm technology node. The notion of this paper is to design and optimization of NSFET with GS high-k gate dielectrics (Al2O3, HfO2, ZrO2 and TiO2) Initially. The switching/analog and RF metric revels that HfO2 is superior in terms SS, switching applications and more compactable with CMOS process. Further, adding number of sheets and temperature variation has been done later. As number of sheets increases, the effective channel width increases, electric field distribution takes place evenly and enhanced gate control owing to improved I O N , I O N / I O F F r a t i o , SS and DIBL. However, increasing the number of vertical channel layers (sheets) more than 2 results into diminished analog/RF performance of JL-NSFET owing to increased parasitic capacitances. Further, the impact of temperature variations (250 K to 450 K) studied for different sheet variations (1 to 5) and noticed that analog/RF such as gm, gds, fT, TFP and GTFP are enhanced by 40.82%, 28.76%, 40.69%, 64.62% and 70.59%, respectively at lower temperature (250 K) when compared to high temperature (450 K). These enhancements make the device is ideal for applications in cryogenic computing systems, satellites, deep space probes, and other aerospace technologies. Furthermore, as the circuit level implementation CMOS inverter and 5-stage ring oscillator (RO) are examined for different sheets and observed as sheets increase delay and EDP increases. For a CMOS inverter the NMH (0.295 V) and NML (0.280 V) are better at 2 sheets with a highest gain of 9.38 V/V. Hence, it is advised to use two or three sheets-based JL-NSFETs for high-performance and lower-power analog/RF applications.

Hypoeutectic Liquid Metal Printing of 2D Indium Gallium Oxide Transistors.

2D native surface oxides formed on low melting temperature metals such as indium and gallium offer unique opportunities for fabricating high-performance flexible electronics and optoelectronics based on a new class of liquid metal printing (LMP). An inherent property of these Cabrera-Mott 2D oxides is their suboxide nature (e.g., In2O3-x), which leads high mobility LMP semiconductors to exhibit high electron concentrations (ne >1019cm-3) limiting electrostatic control. Binary alloying of the molten precursor can produce doped, ternary metal oxides such as In-X-O with enhanced electronic performance and greater bias-stress stability, though this approach demands a deeper understanding of the native oxides of alloys. This work presents an approach for hypoeutectic rapid LMP of crystalline InGaOx (IGO) at ultralow process temperatures (180°C) beyond the state of the art to fabricate transistors with 10X steeper subthreshold slope and high mobility (≈18cm2Vs-1). Detailed characterization of IGO crystallinity, composition, and morphology, as well as measurements of its electronic density of states (DOS), show the impact of Ga-doping and reveal the limits of doping induced amorphization from hypoeutectic precursors. The ultralow process temperatures and compatibility with high-k Al2O3 dielectrics shown here indicate potential for 2D IGO to drive low-power flexible transparent electronics.

Super High-k Unit-Cell-Thick α-CaCr2O4 Crystals.

High-dielectric-constant (high-k) insulators are indispensable components to integrate semiconductors into metal-oxide-semiconductor field-effect transistors with sub-10 nm channel length, where the equivalent oxide thickness (EOT) of high-k insulator needs to be decreased to subnanometer scale. The traditional insulators, including Al2O3, SiO2, and HfO2, fit well with the existing silicon industry but suffer from serious degeneration of insulating properties, such as large leakage currents caused by high-density borders and interface traps, when their thicknesses are reduced to a few nanometers. Here, we synthesize a high-quality nonlayered ultrathin α-CaCr2O4 crystal down to unit-cell thickness (∼1.2 nm) by an elements slow-supply chemical vapor deposition (CVD) method. The unit-cell-thick α-CaCr2O4 crystals show a super high dielectric constant of 87.34, which is over 20 times higher than that of well-known layered insulator h-BN and corresponds to an EOT below 1 nm. Furthermore, it has a high breaking strength (39 GPa) and excellent stability. This strategy can also be used to fabricate other ultrathin ternary oxides, such as high-k ultrathin FeNb2O6 crystals, demonstrating the universality of the CVD method.

Stabilization of Tetragonal Phase in Hafnium Zirconium Oxide by Cation Doping for High-K Dielectric Insulators.

As electronic circuit integration intensifies, there is a rising demand for dielectric insulators that provide both superior insulation and high dielectric constants. This study focuses on developing high-k dielectric insulators by controlling the phase of the Hf0.5Zr0.5O2 (HZO) film with additional doping, utilizing yttrium (Y), tantalum (Ta), gallium (Ga), silicon (Si), and aluminum (Al) as dopants. Doping changes the ratio of tetragonal to monoclinic phases in doped HZO films, and Y-doped HZO (Y:HZO) films specifically exhibit a high tetragonal phase ratio and a dielectric constant of 40.9, indicating superior insulating properties compared to undoped HZO films. To clarify the fundamental mechanism driving the enhancement in dielectric properties, we have carried out various analyses combined with density functional theory (DFT) calculations. Through the optimization of the post-deposition annealing (PDA) process and the heterojunction structure with Al2O3, an Al2O3/Y:HZO heterojunction with a high dielectric constant and even lower leakage current compared to a single layer was developed. The thin-film transistor (TFT) with the Au/Ti/amorphous InGaZnO4 (a-IGZO)/Al2O3/YHZO/TiN heterojunction structure exhibits low subthreshold swing (SS) values within a narrow gate-source voltage (Vsg) range. This study advances knowledge on how the controlled-phase doped HZO films affect the dielectric constant and leakage current and will contribute to semiconductor technology advancements by overcoming the limitations of conventional high-k dielectric insulators.

WS2 Nanosheet-Based Ultrascaled Field-Effect Transistor for Hydrogen Gas Sensing: Addressing the Sensitivity-Downscaling Trade-Off.

In this paper, we propose an ultrascaled WS2 field-effect transistor equipped with a Pd/Pt sensitive gate for high-performance and low-power hydrogen gas sensing applications. The proposed nanosensor is simulated by self-consistently solving a quantum transport equation with electrostatics at the ballistic limit. The gas sensing principle is based on the gas-induced change in the metal gate work function. The hydrogen gas nanosensor leverages the high sensitivity of two-dimensional WS2 to its sur-rounding electrostatic environment. The computational investigation encompasses the nanosensor's behavior in terms of potential profile, charge density, current spectrum, local density of states (LDOS), transfer characteristics, and sensitivity. Additionally, the downscaling-sensitivity trade-off is analyzed by considering the impact of drain-to-source voltage and the electrostatics parameters on subthreshold performance. The simulation results indicate that the downscaling-sensitivity trade-off can be optimized through enhancements in electrostatics, such as utilizing high-k dielectrics and reducing oxide thickness, as well as applying a low drain-to-source voltage, which also contributes to improved energy efficiency. The proposed nanodevice meets the prerequisites for cutting-edge gas nanosensors, offering high sensing performance, improved scaling capability, low power consumption, and complementary metal-oxide-semiconductor compatibility, making it a compelling candidate for the next generation of ultrascaled FET-based gas nanosensors.

Fabrication and electrical properties of flexible polymer-based MIM capacitors of high-k nanolaminate dielectrics of HfO2–SnO2–TiO2 with ultrathin Al2O3 insertion layer by plasma-enhanced atomic layer deposition

Abstract Flexible metal–insulator–metal (MIM) capacitors of high-k nanolaminate HfO2–SnO2–TiO2 thin films were fabricated on several polymer substrates of polyethylene terephthalate, polyimide and epoxy resin at 80 °C by plasma-enhanced atomic layer deposition. The electrical properties were optimized by adjusting the sub-cycle ratio of Hf: Sn: Ti to 6: 5: 4. In order to reduce the leakage current density of flexible capacitors, the ultrathin Al2O3 layer varying from 0.5 to 1.5 nm was inserted to form Al2O3/HfO2–SnO2–TiO2/Al2O3 stacking capacitors. The effect of the Al2O3 insertion layer thickness and the super-cycle number of HfO2–SnO2–TiO2 on the capacitance density, leakage, and quadratic voltage linearity was investigated. Under optimal processing, flexible MIM capacitors could stand 40 000 bending cycles at curvature radius of 8.2 mm, indicative of better electrical stability. Moreover, compared with the polymer-based HfO2–SnO2–TiO2 capacitors, the introduction of 1 nm Al2O3 ultrathin layer greatly decreases the leakage current density by 4 orders of magnitude (10−8 A cm−2) with relative lower voltage linearity (350–540 ppm V−2), but the capacitance density also declines (∼3 fF μm−2) simultaneously. Despite this, the method of inserting Al2O3 ultra-thin layer is still an effective method to improve the electrical performances of polymer-based HfO2–SnO2–TiO2 nanolaminate capacitors for flexible electronics.

Enhanced Oxidation Resistance and Interface Stability of Atomic-Layer-Deposited MoNx Electrodes via TiN Passivation for DRAM Cell Capacitor Applications.

The continuous miniaturization of dynamic random-access memory (DRAM) capacitors has amplified the demand for electrode materials featuring specific characteristics, such as low resistivity, high work function, chemical stability, excellent interface quality with high-k dielectrics, and superior mechanical properties. In this study, molybdenum nitride (MoNx) films were deposited using a plasma-enhanced atomic layer deposition (PEALD) employing bis(isopropylcyclopentadienyl)molybdenum(IV) dihydride and NH3 plasma for DRAM capacitor electrode applications. Depending on the deposition temperatures of the PEALD MoNx films ranging from 200 to 400 °C, the Mo/N ratio and crystal structure varied, transitioning from the cubic NaCl-B1-type MoN phase with Mo/N ratio of 1.4 to the cubic γ-Mo2N phase with Mo/N ratio of 1.9. Notably, MoNx films grown at 400 °C exhibited low resistivity (435 μΩ·cm), a high work function (5.28 eV), and superior mechanical hardness (11.3 GPa) compared to ALD TiN films. Despite these excellent properties, the PEALD MoNx electrode demonstrated insufficient chemical stability, particularly in terms of oxidation resistance and interface quality with ALD HfxZr1-xO2 (HZO) films. This resulted in poor morphology and the formation of significant oxygen-deficient HZO layers (such as HfO2-x), leading to considerable degradation in the electrical performance of metal-insulator-metal (MIM) capacitors. To mitigate this issue, a thin (2.5-14 nm) ALD TiN layer was introduced as a passivation layer between the MoNx bottom electrode and HZO dielectric. The TiN-passivated MoNx (TiN/MoNx) electrode showed substantially enhanced oxidation resistance and reduced interfacial reactions with the HZO dielectric. Consequently, MIM capacitors with TiN/MoNx bottom electrodes demonstrated outstanding electrical performance, including excellent dielectric properties, low leakage current density, and high mechanical strength. Hence, this study proposes a promising candidates for storage nodes in the next-generation DRAM capacitors.

Liquid Metal Oxide-Assisted Integration of High-k Dielectrics and Metal Contacts for Two-Dimensional Electronics.

Two-dimensional van der Waals semiconductors are promising for future nanoelectronics. However, integrating high-k gate dielectrics for device applications is challenging as the inert van der Waals material surfaces hinder uniform dielectric growth. Here, we report a liquid metal oxide-assisted approach to integrate ultrathin, high-k HfO2 dielectric on 2D semiconductors with atomically smooth interfaces. Using this approach, we fabricated 2D WS2 top-gated transistors with subthreshold swings down to 74.5 mV/dec, gate leakage current density below 10-6 A/cm2, and negligible hysteresis. We further demonstrate a one-step van der Waals integration of contacts and dielectrics on graphene. This can offer a scalable approach toward integrating entire prefabricated device stack arrays with 2D materials. Our work provides a scalable solution to address the crucial dielectric engineering challenge for 2D semiconductor-based electronics.

Ultraflat single-crystal hexagonal boron nitride for wafer-scale integration of a 2D-compatible high-κ metal gate.

Hexagonal boron nitride (hBN) has emerged as a promising protection layer for dielectric integration in the next-generation large-scale integrated electronics. Although numerous efforts have been devoted to growing single-crystal hBN film, wafer-scale ultraflat hBN has still not been achieved. Here, we report the epitaxial growth of 4 in. ultraflat single-crystal hBN on Cu0.8Ni0.2(111)/sapphire wafers. The strong coupling between hBN and Cu0.8Ni0.2(111) suppresses the formation of wrinkles and ensures the seamless stitching of parallelly aligned hBN domains, resulting in an ultraflat single-crystal hBN film on a wafer scale. Using the ultraflat hBN as a protective layer, we integrate the wafer-scale ultrathin high-κ dielectrics onto two-dimensional (2D) materials with a damage-free interface. The obtained hBN/HfO2 composite dielectric exhibits an ultralow current leakage (2.36 × 10-6 A cm-2) and an ultrathin equivalent oxide thickness of 0.52 nm, which meets the targets of the International Roadmap for Devices and Systems. Our findings pave the way to the synthesis of ultraflat 2D materials and integration of future 2D electronics.