High-k Spacer Research Articles

The impact of high-k dielectrics on the performance of Schottky barrier source/drain (SBSD) ultra-thin body (UTB) SOI MOSFET

The impact of high-k dielectrics on the performance of Schottky barrier source/drain (SBSD) ultra-thin body (UTB) SOI is investigated in this paper. With the dielectric constants increasing, the on-state currents of SBSD UTB SOI MOSFET decrease, which suggests that the fringing induced barrier lowering (FIBL) is not the major mechanism for the variation of Schottky barrier height. This phenomenon can be understood in terms of the fringing induced barrier shielding (FIBS). It is also shown that the influence of high-k dielectrics on the performance is quite different in the cases that source/drain and gate electrode have an offset or overlap. For the device with an overlap， the structure with a low-k interfacial layer between high-k gate dielectric and substrate is quite effective in suppressing the degradation of drive current due to FIBS. However, for the device with an offset, the combination of high-k dielectric spacer with stack gate can significantly improve the on-state current. This fact can be explained in terms of the refraction of lines of electric force from gate electrode at interfaces of two materials with different dielectric constants. These lines of electric force with refraction can concentrate at the source region, thus lowering the barrier heights and improving the drive currents. Besides, it is shown that on-state current has a local maximum in the case that source/drain and gate electrode has an offset. The structure parameters can be optimized to improve the drive current.

A threshold voltage model for high-k gate-dielectric MOSFETs considering fringing-field effect

In this paper, a threshold voltage model for high-k gate-dielectric metal–oxide-semiconductor field-effect transistors (MOSFETs) is developed, with more accurate boundary conditions of the gate dielectric derived through a conformal mapping transformation method to consider the fringing-field effects including the influences of high-k gate-dielectric and sidewall spacer. Comparing with similar models, the proposed model can be applied to general situations where the gate dielectric and sidewall spacer can have different dielectric constants. The influences of sidewall spacer and high-k gate dielectric on fringing field distribution of the gate dielectric and thus threshold voltage behaviours of a MOSFET are discussed in detail.

Characteristics of High-<tex>$kappa$</tex>Spacer Offset-Gated Polysilicon TFTs

In this paper, a self-aligned offset-gated poly-Si TFT using high-K dielectric (Hafnium oxide, HfO/sub 2/) spacers for channel scaled-down system-on-panel applications is experimentally demonstrated for the first time. The HfO/sub 2/ film is deposited by magnetron sputter deposition, and the HfO/sub 2/ spacers are formed by reactive ion etching. Numerical simulations show that with the high vertical field induced underneath the high-K spacer, an inversion layer is formed, and it effectively increases the on-state current while still maintaining a low leakage current in the off-state, comparing to the conventional lightly doped drain or oxide spacer TFTs. The experimental on-state current in the HfO/sub 2/ spacer offset-gated poly-Si TFT is approximately two times higher than that of the conventional oxide spacer TFT with the same leakage current.

4638252 Circuit for detecting RF coil assembly position in an MR scanner

In analog and RF circuit applications Harmonic distortion (HD) is an important reliability issue that arises due to non-linear performance of devices. In this paper, the asymmetric underlap double gate MOSFET (AUDG-MOSFET) is analyzed for the HD with high-k spacers. In this analysis the devices are compared for their primary distortion components designated by the second order distortion (HD2), the third order distortion (HD3) and the total harmonic distortion (THD). The distortion characteristics of the device are studied as a function of the gate voltage (Vgs) and the transconductance generation factor (gm/Id) considering the influence of drain current (Id) and the transconductance (gm). A significant improvement on the HD of the device by using high-k spacers is inferred, thereby ascertaining better reliability for RF applications. In addition to this, the distortion in the output characteristics of Cascode and differential amplifier circuits designed with AUDG-MOSFET device is also analyzed in detail.