High-k Passivation Layer Research Articles

Analysis of slow-current transients or current collapse in AlGaN/GaN HEMTs with field plate and high-k passivation layer

We study how the dielectric constant of passivation layer εr and field-plate related parameters (its length LFP, passivation-layer thickness Ti) affect the reduction rates of drain current arising from drain lag, gate lag and current collapse in AlGaN/GaN HEMTs. We plot the current-reduction rates versus Ti for different εr. It is indicated that depending on εr, the drain-lag and current-collapse rates take minimum at certain Ti. When εr is 7, 20, 30 and 50, the current-reduction rates become minimum at Ti = 0.03, 0.1, 0.1, and 0.2 μm, respectively. Hence, at the minimum point, εr/Ti which is proportional to capacitance of the passivation layer takes a nearly constant value at 250 ± 50/μm. At this value of Ti, the lags and current collapse are reduced when LFP becomes long for every εr considered here.

Breakdown Voltage Analysis in Quaternary InAlGaN High Electron Mobility Transistor of High-K Passivation Layer for High Power Applications

The 2-Dimensional breakdown characteristics analysis in InAlGaN/GaN high electron mobility transistors (HEMTs) is implemented through including of donor and acceptor atoms inside the barrier layer. Thereby dependences of the relative permittivity εr and the thickness d of passivation layer on the breakdown voltage are related for the parametric analysis. When the relative permittivity εr increases duly affects the breakdown voltage by order of increases, owing to its electric field existence at the drain, there on resulting in εr upsurges. This occurs due to the properties of insulator with the applied voltage evenly drops uniformly. The inducing voltage drop alongside the heterostructure of materials InAlGaN/GaN develops flatter response on the drain terminal of the gate owing to its permittivity εr of higher order. The aforementioned breakdown voltage surges, since of the electric field nearby the drain has weakened as a owing to it thickness of passivating layer d, this resolute InAlGaN/GaN HEMTs of a high-k along with the thicker passivation layer has higher breakdown voltage.

The effect of high-k passivation layer on off-state breakdown voltage of AlGaAs/InGaAs HEMT

In this paper, the effects of different relative permittivity (εr) of the passivation layer on off-state breakdown voltage of AlGaAs/InGaAs HEMTs are analyzed by ISE-TCAD. It is shown that as εr value increases, the off-state breakdown voltage increases. When the εr value increased to 80, the off-state breakdown voltage increased from 17.23V to 24.13V by 40.9%. This is because the peak value of electric field at the proximity of gate edge is reduced with the increase of εr value and it can lead to the improvement of the off-state breakdown voltage of device. Meanwhile, the electric field peak value near the drain edge increases with the increase of the εr value, leading to an increase in the ionization probability of electron-hole ionization under the the grid-drain area. In addition, the results also show that the channel current (IDS) and transconductance (gm) of the device are slightly reduced by the passivation layer with a high εr value, while the specific channel on-resistance is hardly degraded. Therefore, the passivation layer with a high εr value can effectively improve the breakdown voltage of the device without sacrificing the DC characteristics of the device.

Effect of High-k Passivation Layer on High Voltage Properties of GaN Metal-Insulator-Semiconductor Devices

In this paper, the GaN-based MIS-HEMTs with Si <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">3</sub> N <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">4</sub> single-layer passivation, Al <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> O <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">3</sub> /SiN <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">x</sub> bilayer passivation, and ZrO <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> /SiN <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">x</sub> bilayer passivation are demonstrated. High-k dielectrics are adopted as the passivation layer on MIS-HEMTs to suppress the shallow traps on the GaN surface. Besides, high permittivity dielectrics passivated MIS-HEMTs also show an improved breakdown voltage characteristic, and that is explained by 2-D simulation analysis. The fabricated devices with high-k dielectrics/SiN <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">x</sub> bilayer passivation exhibit higher power properties than the devices with plasma enhanced chemical vapor deposition-SiNx single layer passivation, including smaller current collapse and higher breakdown voltage. The Al <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> O <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">3</sub> /SiN <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">x</sub> passivated MIS-HEMTs exhibit a breakdown voltage of 1092 V, and the dynamic R <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">on</sub> is only 1.14 times the static R <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">on</sub> after off-state VDS stress of 150 V. On the other hand, the ZrO <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> /SiN <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">x</sub> passivated MIS-HEMTs exhibit a higher breakdown voltage of 1207 V, and the dynamic Ron is 1.25 times the static R <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">on</sub> after off-state VDS stress of 150 V.

Numerical analysis of the reverse blocking enhancement in High-K passivation AlGaN/GaN Schottky barrier diodes with gated edge termination

We conducted a numerical analysis on high-K dielectric passivated AlGaN/GaN Schottky barrier diodes (HPG-SBDs) with a gated edge termination (GET). The reverse blocking characteristics were significantly enhanced without the stimulation of any parasitic effect by varying the dielectric thickness dge under the GET, thickness TP, and dielectric constant εr of the high-K passivation layer. The leakage current was reduced by increasing εr and decreasing dge. The breakdown voltage of the device was enhanced by increasing εr and TP. The highest breakdown voltage of 970 V and the lowest leakage current of 0.5 nA/mm were achieved under the conditions of εr = 80, TP = 800 nm, and dge = 10 nm. C-V simulation revealed that the HPG-SBDs induced no parasitic capacitance by comparing the integrated charges of the devices with different high-K dielectrics and different dge.

Effects of acceptors in a Fe-doped buffer layer on breakdown characteristics of AlGaN/GaN high electron mobility transistors with a high-k passivation layer

We analyze off-state breakdown characteristics of AlGaN/GaN high electron mobility transistors (HEMTs) with a Fe-doped buffer layer where a deep acceptor located above the midgap is included. It is shown that by introducing a high-k passivation layer, the breakdown voltage Vbr improves as in a case with an undoped semi-insulating buffer layer. In the Fe-doped case, Vbr becomes a little higher in the case where the passivation layer’s relative permittivity εr is rather higher when the energy levels determining the Fermi level are set equal in the two buffers. It is also shown that when the energy level of deep acceptor is deeper, Vbr becomes higher in the region where εr is high. This occurs because the leakage current via the buffer layer becomes smaller.

Simulation design of high reverse blocking high-K/low-K compound passivation AlGaN/GaN Schottky barrier diode with gated edge termination

In this paper, a novel high-K/low-K compound passivation AlGaN/GaN Schottky Barrier Diode (CPG-SBD) is proposed to improve the off-state characteristics of AlGaN/GaN schottky barrier diode with gated edge termination (GET-SBD) by adding low-K blocks in to the high-K passivation layer. The reverse leakage current of CPG-SBD can be reduced to 1.6 nA/mm by reducing the thickness of high-K dielectric under GET region to 5 nm, while the forward voltage and on-state resistance keep 1 V and 3.8 Ω mm, respectively. Breakdown voltage of CPG-SBDs can be improved by inducing discontinuity of the electric field at the high-K/low-K interface. The breakdown voltage of the optimized CPG-SBD with 4 blocks of low-K can reach 1084 V with anode to cathode distance of 5 μm yielding a high FOM of 5.9 GW/cm2. From the C-V simulation results, CPG-SBDs induce no parasitic capacitance by comparison of the GET-SBDs.

Design of high breakdown voltage vertical GaN p-n diodes with high-K/low-K compound dielectric structure for power electronics applications

In this work, a vertical GaN p-n diode with a high-K/low-K compound dielectric structure (GaN CD-VGD) is proposed and designed to achieve a record high breakdown voltage (BV) with a low specific on-resistance (Ron,sp). By introducing compound dielectric structure, the electric field near the p-n junction interface is suppressed due to the effects of high-K passivation layer, and a new electric field peak is induced into the n-type drift region, because of a discontinuity of electrical field at the interface of high-K and low-K layer. Therefore the distribution of electric field in GaN p-n diode becomes more uniform and an enhancement of breakdown voltage can be achieved. Numerical simulations demonstrate that GaN CD-VGD with a BV of 10650 V and a Ron,sp of 14.3 mΩ cm2, resulting in a record high figure-of-merit of 8 GW/cm2.

The influence of high-k passivation layer on breakdown voltage of Schottky AlGaN/GaN HEMTs

In this work, analysis and optimization of different high-k material in the passivation layer is carried out to improve the breakdown voltage in a Schottky based AlGaN/GaN High Electron Mobility Transistor (HEMT). The enhancement in Off-state breakdown voltage is observed for different high-k dielectric in the passivation layer. The device with Lgd of 1.5µm and with high-k passivation layer provides a higher Off-state breakdown voltage. A maximum of 380V is obtained as the Off-state breakdown for high-k (~HfO2) passivation layer and the obtained result is validated using experimental data. The improved drain current and transconductance for the device obtained is 0.51A/mm and 143mS/mm respectively. These results show that the Schottky Source Drain contact (SSD) high-k passivated AlGaN/GaN device is suitable for high power application.

Effects of buffer leakage current on breakdown characteristics in AlGaN/GaN HEMTs with a high-k passivation layer

A two-dimensional analysis of off-state breakdown characteristics in AlGaN/GaN HEMTs is performed by considering a deep donor and a deep acceptor in a buffer layer, with the relative permittivity of passivation layer εr as a parameter. The analysis is made with and without impact ionization of carriers to study how the buffer leakage current affects the breakdown performance. It is shown that when εr is low, the breakdown voltage is determined by the impact ionization of carriers, and when εr becomes high, it is determined by the buffer leakage current. This buffer leakage current decreases as εr increases because the electric field at the drain edge of the gate is weakened, and hence the breakdown voltage increases as εr increases. It is also shown that when the gate voltage is more negative, the breakdown voltage in the high εr region becomes higher because the buffer leakage current becomes smaller.

Analysis of high-k passivation-layer effects on buffer-related breakdown and current collapse in AlGaN/GaN HEMTs

We analyze breakdown characteristics and current collapse in AlGaN/GaN HEMTs, with the passivation layer’s relative permittivity εr as a parameter. It is shown that the off-state breakdown voltage is considerably enhanced by introducing a high-k passivation layer because the electric field at the drain edge of the gate is weakened and the buffer leakage current is reduced. The breakdown voltage in the high-εr region increases when the gate voltage is changed from −8 to −10 V, because the buffer leakage current is reduced. It is also shown that drain lag and current collapse in AlGaN/GaN HEMTs could be reduced by introducing a high-k thick passivation layer, because the electric field at the drain edge of the gate is reduced, leading to less electron injection into the buffer layer and weaker buffer trapping effects.

High breakdown voltage AlGaN/GaN HEMT with high‐K/low‐K compound passivation

A novel high breakdown voltage (BV) AlGaN/GaN high-electron mobility transistor (HEMT) with a high-K/low-K compound passivation layer is proposed. The compound passivation layer is formed by blocks of low-K dielectric (Si3N4) embedded in a high-K passivation layer (La2O3). Owing to their different dielectric constants, there is a discontinuity of the horizontal electrical field at the high-K/low-K interface, which can introduce a new electric field peak in the nearby channel in the semiconductor and can also modulate the distribution of the electric field along the channel. Hence, enhancement of BV can be achieved. Compared to the typical field-plate structure, high-K/low-K passivation introduces no parasitic capacitance. On the basis of the physical mechanism, several design principles for the high-K/low-K passivation layer are presented. Numerical simulation demonstrates a BV of 1400 V for the proposed device with four blocks of low-K dielectric embedded in a high-K passivation, compared to the BVs of 917 and 288 V for the device with high-K passivation and the device with low-K passivation, respectively.

Low-frequency noise in multilayer MoS2field-effect transistors: the effect of high-k passivation

Diagnosing of the interface quality and the interactions between insulators and semiconductors is significant to achieve the high performance of nanodevices. Herein, low-frequency noise (LFN) in mechanically exfoliated multilayer molybdenum disulfide (MoS2) (~11.3 nm-thick) field-effect transistors with back-gate control was characterized with and without an Al2O3 high-k passivation layer. The carrier number fluctuation (CNF) model associated with trapping/detrapping the charge carriers at the interface nicely described the noise behavior in the strong accumulation regime both with and without the Al2O3 passivation layer. The interface trap density at the MoS2-SiO2 interface was extracted from the LFN analysis, and estimated to be Nit ~ 10(10) eV(-1) cm(-2) without and with the passivation layer. This suggested that the accumulation channel induced by the back-gate was not significantly influenced by the passivation layer. The Hooge mobility fluctuation (HMF) model implying the bulk conduction was found to describe the drain current fluctuations in the subthreshold regime, which is rarely observed in other nanodevices, attributed to those extremely thin channel sizes. In the case of the thick-MoS2 (~40 nm-thick) without the passivation, the HMF model was clearly observed all over the operation regime, ensuring the existence of the bulk conduction in multilayer MoS2. With the Al2O3 passivation layer, the change in the noise behavior was explained from the point of formation of the additional top channel in the MoS2 because of the fixed charges in the Al2O3. The interface trap density from the additional CNF model was Nit = 1.8 × 10(12) eV(-1) cm(-2) at the MoS2-Al2O3 interface.

Performance Improvement of Polycrystalline Silicon Nanowire Thin-Film Transistors by a High-k Capping Layer

In this work, a novel polycrystalline silicon (poly-Si) nanowire thin-film transistor (NW-TFT) with side-gated configuration and a high-k material capping was fabricated and characterized. It was found that the gate fringing field effect via the high-k passivation layer can effectively improve the device performance in terms of higher ON current, larger ON/OFF current ratio, and steeper subthreshold slope (SS). The drain-induced barrier lowering (DIBL) effect is also effectively suppressed owing to better gate control.