High-k Gate Dielectric Material Research Articles

Retraction Note: Exploring High-Temperature Reliability of 4H-SiC MOSFETs: A Comparative Study of High-K Gate Dielectric Materials

Retraction Note: Exploring High-Temperature Reliability of 4H-SiC MOSFETs: A Comparative Study of High-K Gate Dielectric Materials

Quantum transport in WSe2/SnSe2 tunneling field effect transistors with high-k gate dielectrics

Combining two-dimensional materials and high-k gate dielectrics offers a promising way to enhance the device performance of tunneling field-effect transistor (TFET). In this work, the device performance of WSe2/SnSe2 TFET with various gate dielectric materials is investigated based on quantum transport simulation. Results show that TFETs with high-k gate dielectric materials exhibit improved on-off ratio and enhanced transconductance. The optimized WSe2/SnSe2 TFET with TiO2 gate dielectrics achieves an on-state current of 1560 μA/μm and a subthreshold swing (SS) of 48 mV/dec. The utilization of high-k gate dielectric materials results in shorter tunneling length, higher transmission efficiency, and increased electron tunneling probability. The performance of the WSe2/SnSe2 TFET would be affected by the presence of the underlap region. Moreover, WSe2/SnSe2 TFETs with La2O3 dielectric can be scaled down to 3 nm while meeting high-performance (HP) device requirements according to the International Technology Roadmap for Semiconductors (ITRS). This research presents a practical solution for designing advanced logic devices in the sub-5 nm technology node.

Exploring High-Temperature Reliability of 4H-SiC MOSFETs: A Comparative Study of High-K Gate Dielectric Materials

Exploring High-Temperature Reliability of 4H-SiC MOSFETs: A Comparative Study of High-K Gate Dielectric Materials

Enhancing Performance of Dual-Gate FinFET with High-K Gate Dielectric Materials in 5 nm Technology: A Simulation Study

Enhancing Performance of Dual-Gate FinFET with High-K Gate Dielectric Materials in 5 nm Technology: A Simulation Study

Interfacial band parameters of ultrathin ALD-ZrO2 on Ga-polar GaN through XPS measurements

Recent demonstrations of grafted p-n junctions combining n-type GaN with p-type semiconductors have shown great potential in achieving lattice-mismatch epitaxy-like heterostructures. Ultrathin dielectrics deposited by atomic layer deposition (ALD) serve both as a double-sided surface passivation layer and a quantum tunneling layer. On the other hand, with excellent thermal, mechanical, and electrical properties, ZrO2 serves as a high-k gate dielectric material in multiple applications, which is also of potential interest to applications in grafted GaN-based heterostructures. In this sense, understanding the interfacial band parameters of ultrathin ALD-ZrO2 is of great importance. In this work, the band-bending of Ga-polar GaN with ultrathin ALD-ZrO2 was studied by x-ray photoelectron spectroscopy (XPS). This study demonstrated that ZrO2 can effectively suppress upward band-bending from 0.88 to 0.48 eV at five deposition cycles. The bandgap values of ALD-ZrO2 at different thicknesses were also carefully studied.

(Invited) Advances in Atomic Layer Processing of Hafnia-Zirconia Ferroelectrics

The limits of integrating ferroelectric materials on commercial semiconductor chips were demolished the moment ferroelectricity in hafnia and zirconia films was reported in 2011. This breakthrough moment in the history of ferroelectric materials was made possible by the fortuitous interplay between advances in atomic layer processing and the strong surface energy dependence of crystal phases in HfO2 and ZrO2. Aided by commercial investment in using both materials as high-k gate and DRAM dielectric materials, atomic layer deposition (ALD) processes are beginning to take full advantage of the completely solid-soluble hafnia-zirconia (Hf1-xZrxO2) ferroelectric system with new precursors and new insights obtained by systematically evaluating film growth conditions. The capability to precisely adjust the compositional profile and to alter oxidation conditions during atomic layer deposition film growth are giving an unprecedented level of control to engineer Hf1-xZrxO2 and doped HfO2 thin films for ferroelectric applications.The latest advances in atomic layer processing of Hf1-xZrxO2 and doped-HfO2 are presented where the dynamic interaction between composition and film growth conditions provide an engineering roadmap to adjust the physical and structural properties of the dielectric films. Metal precursors play a crucial role in the ensuing film properties. The adjustability of the electrical and structural properties of Hf1-xZrxO2 with ozone exposure during ALD film growth is discussed with respect to the important role oxygen and oxygen vacancies have in the overall phase stability of these novel ferroelectric materials, as well as C incorporation caused by ALD precursors. Just as atomic layer deposition has proven to be instrumental in the discovery and stabilization of the ferroelectric phase in HfO2-based thin films, atomic layer etching (ALE) of HfO2/ZrO2-based layers is now being used to preserve ferroelectricity while pushing the thickness dimension to new limits, yielding high performance films for ferroelectric tunnel junction applications. Further innovations in atomic layer processing will continue to be a harbinger of high performance ferroelectrics in the coming years based on the current status and future outlook for ferroelectric Hf1-xZrxO2 and other emerging ferroelectric materials.

Impact of High-K Gate Dielectric Materials on Uniformly Doped Dual Gate FinFET for Analog and Digital Applications

Impact of High-K Gate Dielectric Materials on Uniformly Doped Dual Gate FinFET for Analog and Digital Applications

Design, simulation and analysis of high-K gate dielectric FinField effect transistor

The devices with additional gates like Fin Field effect transistor (FinFET) provide higher control on subthreshold parameters and are favorable for Ultra large-scale integration. Also, these structures provide high control on current through the channel and with minimum leakage. In this paper we designed a FinFET with high-K gate dielectric material i.e Hafnium oxide as gate oxide. A comparison of similar sized transistor with Air and Silicon dioxide as gate material is performed. The comparison is mainly in terms of performance parameters like transconductance, subthreshold slope, and drain current characteristics. There is an increase in ON current on using a high-K dielectric material and subsequently an improvement in other parameters like subthreshold slope, transconductance and intrinsic gain.

Low Power Circuit and System Design Hierarchy and Thermal Reliability of Tunnel Field Effect Transistor

Tunnel FET is one of the promising devices advocated as a replacement of conventional MOSFET to be used for low power applications. Temperature is an important factor affecting the performance of circuits or system, so temperature associated reliability issues of double gate Tunnel FET and its impact on essential circuit design components have been addressed here. The temperature reliability investigation is based on double gate Tunnel FET, containing Si1-xGe x /Si, source/channel and HfO2 high-k gate dielectric material. During investigation, it has been found that at high temperature application range ~ 300 K - to - 600 K,the Tunnel FET device design parameters exhibit weak temperature dependency with switching current (ION), while the off-state current (IOFF) is slightly varying ~10−17A/μm-to-10−10A/μm. In addition, the impact of temperature on various device design element such as VTH(i.e.,switching voltage),on-current (ION), off-current (IOFF), switching ratio (ION/IOFF) and average subthreshold slope (i.e., SSavg), ambipolar current (IAMB) have been done in this research work.The essential circuit design components for digital and analog/RF applications, such as current amplification factor(gm) and its derivative (gm’),the C-V components of device design, Cgg, Cgd and Cgs, cut - off frequency (ƒT) and gain band width (GBW) product have deeply investigated. In conclusion, the obtained results show that the designed double gate Tunnel FET device configuration and its circuit design components are suitable for ultra-low power circuit,system applications and reliable for hazardous temperature environment.

Triple Metal Surrounding Gate Junctionless Tunnel FET Based 6T SRAM Design for Low Leakage Memory System

The promising capability of Triple Material Surrounding Gate Junctionless Tunnel FET (TMSG – JL – TFET) based 6 T SRAM structure is demonstrated by employing Germanium (Ge) and High-K gate dielectric material. The high – K insulation guarantees the proposed device to be used in low leakage memory systems. The corresponding analytical model is developed to extract various device parameters such as surface potential, electric field and threshold voltage. The results yield minimization of hot carrier effects at the drain end, when compared to conventional Silicon (Si) based Tunnel FETs (TFETs). Further, the ambipolar characteristics of the proposed device is explored and 6 T Ge – TMS – SG – JL – TFET based SRAM design is proposed. The results are compared with CMOS based SRAM and the analytical model presented is validated using 3D - TCAD ATLAS simulation, which ensures the accuracy and exactness of the developed model.

Novel modification in evanescent mode analysis to incorporate sub-1 nm equivalent oxide thickness in the subthreshold model of junctionless asymmetric double gate FETs

A novel modification in the evanescent mode analysis is presented in this work to comprehend the implication of a high gate dielectric constant in the subthreshold model of junctionless (JL) asymmetric double gate (DG) FETs. A brief study is presented to highlight the lack of an appropriate device model for the JL FET with a sub-1 nm equivalent oxide thickness. This work elaborates the effect of a high-k gate dielectric on one of the most important parameters of evanescent mode analysis, known as the inverse characteristics length. Thereby, an appropriate modification is incorporated in the widely adopted evanescent mode analysis to develop the subthreshold model compatible with high-k gate-dielectric materials and sub-1 nm gate-oxide thickness. Subsequently, the subthreshold model of DG FET with a high-k gate dielectric is presented. The DG FET assumes gate-oxide asymmetry as well as channel doping asymmetry arising due to the ion-implantation and subsequent annealing. With the help of the developed model, the subthreshold characteristics of the device are studied with the variations in device dimensions, the gate-dielectric constant, the doping profile, etc. The results have been found to be in good agreement when numerically studied in comparison with the outcomes of the Synopsys Sentaurus™ Device simulation tool.

Simulations of the CNFETs using different high-k gate dielectrics

In this paper we presented the analysis of Carbon Nanotube Field Effect Transistors (CNFETs) using various high-k gate dielectric materials. The objective of this work was to choose the best possible material for gate dielectric. This paper also presented the study on the effect of thickness of gate dielectric on the performance of the device. For the analysis (19, 0) CNT was considered because the diameter of (19, 0) CNT is 1.49nm and the CNFETs have been fabricated with the CNT diameter of ~1.5nm. It has been observed that La2O3 is the best gate dielectric material followed by HfO2 and ZrO2. It was also observed that as thickness of gate dielectric material reduces, drain current of CNFET increases. The outcomes of this study matches with the analytical results and hence confirm the results

(Invited) Ferroelectric Materials Study Using First-Principles Calculations and Materials Informatics

In the past a couples of decades, first-principles calculation has become powerful tool for materials study. In our group, ferroelectric material is one of important research target.Softmodes and the structural phase transitions associated with them are is one of most important research topic in the field of ferroelectric materials. In the 2000s, a technique for calculating phonon using first-principles calculations was developed. Since then, softmode in ferroelectric materials have been extensively studied by many groups. More reentry, an automated method for comprehensive softmode analysis using simple algorithm for automated searching of phase-transition pathways based upon first-principles phonon calculations has been developed by Togo and Tanaka.[1] Figuer1(a) shows how the procedure is composed of multiple calculation “units.” Each calculation takes a crystal structure as its input. The initial structure is relaxed under the constraints of its crystal symmetry, i.e., during relaxation no lowering of crystal symmetry is allowed. However, increase in symmetry is allowed and often occurs. In such higher symmetry cases, the space group of the crystal structure may not be a subgroup of the space group of the initial structure, but it is a subgroup of the space group of the relaxed (final) structure. The dynamical stability of the final structure is then examined by calculate supercell force constant. If any instabilities are found, the structure is deformed along the relevant direction. These calculations are repeated until all of softmodes are eliminated.Using this procedure, we can examine the mechanisms of softmode related structural phase transitions. Another advantage of this method is that it allows phase transition pathway via metastable structures to be proved, which may enable. Possible phase transition pathways are difficult to determine to be discovered experimentally. Fluorite structured hafnia (HfO2) is used as a high-k gate dielectric material in Si semiconductor devices. Recently, the ferroelectric behavior of thin film HfO2 has been reported. However, the origin and mechanism of this ferroelectric phase transition are still not well understood. Identifying the origin of this ferroelectricity would allow hafnia-based materials to be developed for application in nonvolatile memories and ferroelectric field effect transistors. Hence, in this study, we have attempted to elucidate the mechanism of the ferroelectric phase transition in thin-film HfO2 by performing comprehensive softmode analysis.Our results are summarized in Fig.1(b). Under ambient pressure, no softmode is observed for the tetragonal P42/nmc phase. However, under slight negative (tensile) pressure (-3 GPa), a softmode leading resulting in a transition to the experimentally observed ferroelectric Pca21 phase was found. This softmode path is sensitive to pressure, as it vanished we applying positive (compressive) pressure, or zero pressure. In thin film form, the volume change HfO2 need to undergo during the first-order phase transition from tetragonal to monoclinic is suppressed by the constraining substrate. Under these condition, a ferroelectric phase transition through this softmode path can occur.[2] References [1] A. Togo and I. Tanaka, Phys. Rev. B, 87, 184104 (2013).[2] H. Moriwake, A. Taguchi, C.A.J. Fisher, A. Togo, T. Shimizu, H. Funakubo, in preparation. Figure 1

Effects of High-k Dielectric Materials on Electrical Performance of Double Gate and Gate-All-Around MOSFET

This paper presents the electrical behaviour of Double Gate (DG) and Gate-All-Around nanowire (GAA) MOSFET using different high permittivity (high-k) gate dielectric materials. In order to study the influence of high- k dielectric material towards DG and GAA, Atlas Silvaco TCAD tools were used to simulate the device and to determine the electrical characteristics. The high-k materials chosen in this study were Silicon Nitride (Si3N4), Aluminium Oxide (Al2O3), Zirconium Oxide (ZrO2) and Hafnium Oxide (HfO2). The gate dielectric materials have played a significant role in the design of novel and high performances at nanoscale of electrical devices. It can be observed that when approaching a higher value of dielectric constant, the on current increases while the subthreshold slope (SS) threshold voltage (Vth) and leakaga current reduced. It can be observed that HfO2 shows the best performance compared to other simulated dielectric materials for both DG and GAA MOSFET.

Novel high-k gate dielectric properties of ultrathin hydrocarbon films for next-generation metal-insulator-semiconductor devices

New high-k gate dielectrics are highly necessary in facilitating the continuous down-scaling of metal–oxide–semiconductor devices to the sub-10 nm range. This study presents ultrathin organic hydrocarbon (HC) films as a novel high-k gate insulator for metal–insulator–semiconductor (MIS) devices. During inductively-coupled plasma chemical vapor deposition with CH4 and H2 gases, the growth temperature greatly affects the structure of the carbon layers and consequently their dielectric characteristics. Specifically, sp2-rich dielectric HC layers are formed below 600 °C, whereas highly-ordered sp2-hybridized graphene is formed at 950 °C. The k value of the resulting HC films increases up to a maximum value of 90 at 350 °C. Moreover, the MIS devices exhibit excellent gate-insulating properties, including almost no hysteresis in the capacitance–voltage curve, low leakage current, and high dielectric strength, which surpass those of existing high-k gate oxides. These results reveal that the organic HC films are a promising next-generation high-k gate dielectric material for sub-10 nm node Si and organic semiconductor technologies.

Fabrication and Characterization of amorphous Lanthanum Zirconate Gate Capacitors

A novel high-k gate dielectric material, i.e., Lanthanum-doped Zirconium oxide (La-doped ZrO2), has been thoroughly studied for applications in future metal oxide semiconductor field-effect transistor (MOSFET). The film's structural, chemical and electrical properties are investigated experimentally. The incorporation of La into ZrO2 impacted the electrical properties in terms of leakage current while not sacrificing its dielectric constant. The dielectric constant of 25 is achieved which is calculated from the C-V analysis taken from Agilent 1500A Semiconductor Device Analyzer. XRD, FTIR, EDX analysis were conducted to confirm the stoichiometry and bond formation of La2Zr2O7. The sol-gel spin coating method is adopted to form a uniform thin film over p-Silicon substrate and Aluminium is evaporated in the eBeam technique as gate electrode to form an MIS capacitor. The La-doped ZrO2 film is hence a potential high-k gate dielectric for future application in MIS thin film transistors.

High-k Fluoropolymer Gate Dielectric in Electrically Stable Organic Field-Effect Transistors.

A detailed study of a high-k fluoropolymer gate dielectric material, poly(vinylidene fluoride- co-hexafluoropropylene) [P(VDF-HFP)], is presented as a guide to achieve low operational voltage and electrically stable device performance. The large dipole moment of C-F dipoles in P(VDF-HFP) is responsible for its high dielectric constant as well as its potentially ferroelectric behavior that must be minimized to avoid hysteretic current-voltage characteristics. A range of material grades and processing conditions are explored and are shown to have a significant effect on the degree of hysteresis observed in device-transfer characteristics. The percentage of HFP monomer in the P(VDF-HFP) dielectric has an effect on gate-dependent mobility induced by disorder at the semiconductor-dielectric interface. Most importantly, we present the considerations that must be made to achieve optimal performance in multiple device architectures of organic field-effect transistors when using P(VDF-HFP) as a dielectric layer.

Annealing effect and leakage current transport mechanisms of high k ternary GdAlOx gate dielectrics

In this work, ternary GdAlOx (GAO) thin films as new gate dielectric materials were offered by magnetron sputtering. The microstructure, band gap and electrical properties of ternary GAO gate dielectric thin films as functions of annealing temperatures were measured. It can be noted that annealing at 600 °C for 6 min in oxygen atmosphere is the best annealing process. And GAO thin films annealed at 500 °C–800 °C still express their amorphous state, showing excellent thermal stability. In addition, the films annealed at 600 °C have a maximum band gap of 5.36 eV. Electrical properties of all samples based on Pt/GAO/Si/Pt metal-oxide-semiconductor (MOS) capacitors have been investigated and they have been characterized by capacitance-voltage (C-V) and leakage current density-voltage (I-V) curves. Results show that the samples annealed at 600 °C display excellent performance such as highest dielectric constant (k) of 21.2 and lowest current density of 4.94 × 10−3A/cm2 at Vfb-1 V. Therefore, the GAO thin films annealed at 600 °C can be used as one of candidate high-k gate dielectric materials in future. Finally, the leakage current transport mechanisms of all Pt/GAO/Si/Pt MOS capacitors have been discussed in detail.

New dual material double gate junctionless tunnel FET: Subthreshold modeling and simulation

A subthreshold analytical model for Dual Material Double Gate Junctionless Tunnel FET (DMDG JLTFET) is developed. To analyze the behavior of short channel device, relevant parameters such as surface potential, electric field, threshold voltage, drain current, transconductance-to-drain current ratio, subthreshold slope and subthreshold swing are extracted from the 2-D analytical solution of Poisson's equation. Relating DMDG JLTFET to Junctionless MOSFETs, the results show significant reduction of Short Channel Effects (SCEs) at the drain end. The analytical model for DMDG JLTFET is effective due to the combined supremacy of uniform doping in the channel, usage of high-K gate dielectric material and work function engineering in the gate metal. The results obtained from the analytical model are simulated and validated using 2-D Sentaurus TCAD device simulator.

Carrier Transport Mechanism via a High-k HfO₂ Thin Layer Between GaAs Layers.

Carrier transport mechanisms via a high-k gate dielectric material of hafnium dioxide (HfO2) between III-V GaAs were investigated by using a non-equilibrium Green's function (NEGF). The full band structure for the HfO2 layer was determined by using a sp3d5s* closest neighbor empirical tight-binding model. The band structure of the GaAs bulk was determined by using an empirical tight-binding model. The tunneling currents dependent on the thickness of the HfO2 layer with a GaAs layer were obtained by solving the NEGF in an open boundary condition. The applied voltage to obtain the tunneling currents through the HfO2 layer between the GaAs layers was higher than that for the Si/HfO2/Si structure. This was due to the much smaller energy difference between the conduction band edge (Ec) and the Fermi level (Ef) of the Si layer than that of the GaAs layer. The GaAs/HfO2/GaAs structure showed an increase in the leakage current in comparison with the Si/HfO2/Si structure.