High-k Devices Research Articles

Coherent Epitaxy of HfxZr1-xO2 Thin Films by High-pressure Magnetron Sputtering

Due to remarkable high-k and ferroelectric properties in CMOS devices, the study of crystalline HfxZr1-xO2 (HZO) thin films has attracted tremendous interest recently. However, up to now, the epitaxial growth of HZO films has only been achieved by pulse laser deposition, a technique scarcely utilized in CMOS devices. Therefore, developing appropriate epitaxial methods of HZO films (such as sputtering) is fairly necessary, but a challenge at present. In this work, high-quality single-crystalline HZO films were synthesized by high-pressure magnetron sputtering. The epitaxial growth of HZO films on yttria-stabilized zirconia (YSZ) substrate was demonstrated by a combination of high-resolution X-ray diffraction, atom force microscope, and scanning transmission electron microscope. In addition, good insulating characteristics were obtained by replacing insulating substrates with conductive substrates as electrodes. Our results provide a novel way for the epitaxial growth of the single-crystalline structure of HZO thin films towards the high performance of high-k and ferroelectric devices.

Ultrafast ID – VG Technique for Reliable Cryogenic Device Characterization

An in-depth understanding of the transient operation of devices at cryogenic temperatures remains experimentally elusive. However, the impact of these transients has recently become important in efforts to develop both electronics to support quantum information science as well as cryogenic high-performance computing. In this paper, we discuss a fast time-dependent device characterization technique, capable of examining the charge trapping dynamics of devices operating at cryogenic temperatures. Careful calibrations allow for the acquisition of accurate fast I-V and transconductance transients down to 20 ns for devices operating down to 8 K. The trap charging dynamics was monitored via shifts in both threshold voltage and transconductance. The combination of fast measurements and cold temperatures were used to shift the observable measurement window to reveal charge trapping/de-trapping time dynamics of both fast and slow traps in high-k devices to demonstrate the utility of the fast I-V for cryogenic device characterization.

Improving the Scalability of Ferroelectric FET Nonvolatile Memories With High-k Spacers

This paper investigates scaled ferroelectric field-effect transistor (FeFET) nonvolatile memories (NVMs) with high-k spacer device design considering ferroelectric-dielectric random phase variations with TCAD atomistic simulations. Our study indicates that, in addition to raising the orthorhombic phase and reducing the grain size of the ferroelectric, using high-k spacers can serve as another way to enhance the scalability of FeFETs because it improves both the mean memory window (MW) and the worst-case MW. More importantly, these improvements increase with the down-scaling of gate length. In addition, we have investigated the impact of high-k spacers on the critical electric field across interfacial layer (EIL) for the reliability of FeFET NVMs. Our study suggests that, for scaled FeFETs with high-k spacers, the highest EIL during write operation is no longer located near the S/D edge but at the mid channel. Using high-k spacers can reduce the mid-channel EIL, and the reduction increases with decreasing gate length due to the increasing impact of high-k spacers. Our study may provide insights for future high-density FeFET design.

Improving Breakdown Voltage in AlGaN/GaN Metal-Insulator-Semiconductor HEMTs Through Electric-Field Dispersion Layer Material Selection

In this work, three MISHEMT devices with different electric-field-dispersion layer (EDL) behave the same pristine electrical properties. EDL, which is low dielectric constant (low-k), can effectively disperse electric field, which enhances breakdown voltage and improves reliability in MISHEMT. In a comparison of devices with high-k and low-k EDL, the on-state current ( <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\text{I}_{\mathrm{ on}}$ </tex-math></inline-formula> ) of the high-k EDL devices is more significantly reduced than low-k EDL devices after off-state stress. A model for the dispersion of electric fields by the EDL is proposed for this interesting phenomenon. The distribution of the electric field is verified by Silvaco electric field simulation. Finally, the breakdown voltages of the three devices were measured, confirming that the devices with a low-k EDL can increase their breakdown voltages by an additional 600 V, which is 250 % higher than that in the high-k EDL device.

Shallow electron traps in high-k insulating oxides

In the present work the use of low temperature (77 K) charge injection and thermally activated emission is proposed as a universal method for characterization of shallow traps in high permittivity insulating oxides (HfO2, ZrO2, LaSiOx). A broad temperature range (77 K–300 K) allows one to evaluate density and energy distribution of electron traps within the energy depth range ≈1 eV below the oxide conduction band. The volume concentration of these traps is found to be in the range of 1019–1020 cm−3 in all studied materials indicating that shallow trapping will significantly affect performance of the high-k oxide-based devices operating at low temperature and/or very short pulse times.

Numerical study on the self-heating effects for vacuum/high-k gate dielectric tri-gate FinFETs

The self-heating effects (SHEs) for Vacuum Gate Dielectric (VGD) tri-gate FinFET compared with High-k (HK) Dielectric tri-gate FinFET were investigated here based on 3D numerical electro-thermal TCAD simulation method. Simulation results show that VGD device suffers from a fiercer SHEs than HK device which will result in larger saturation current degradation. It is due to the low thermal conductivity of the gas around the channel which impedes the heat diffusion to the sinks and increases the peak temperature in the hot spot region. The SHEs can be suppressed by increasing the width of gas gap and gas pressure, based on the analysis of the pressure-dependent thermal conductivity of the gas in Nano-gap. However, the increased gas gap width entails the loss of the gate control ability over the channel resulting in the severer short channel effects.

Blocking of deuterium diffusion in poly-Si/Al2O3/HfxSi1−xO2/SiO2 high-k stacks as evidenced by atom probe tomography

Hydrogen (H) plays an important role in determining the reliability and performance of HfO2- and Al2O3-based high-k dielectric electronic devices. In order to understand H behavior, deuterium (D), an isotope of H, was introduced into the poly-Si cap of Al2O3/HfxSi1−xO2/SiO2 high-k stacks by ion implantation. Atom probe tomography was used to image the D distribution in samples annealed under different conditions. The results clearly demonstrated that the D atoms were trapped at the interface of poly-Si and Al2O3 after annealing at 900 K for 10 min. Thus, it is possible that Al2O3 blocks the H atoms at the surface, preventing them from diffusing into the high-k dielectrics during the H2 annealing process in current fabrication technology. The current work also exhibits an example of investigating H behavior in semiconductors by atom probe tomography.

Reliability of Metal Gate / High-k devices and its impact on CMOS technology scaling

ABSTRACTMG/HK was introduced into CMOS technology and enabled scaling beyond the 45/32nm technology node. The change in gate stack from poly-Si/SiON to MG/HK introduced new reliability challenges like the positive bias temperature instability (PBTI) and stress induced leakage currents (SILC) in nFET devices which prompted thorough investigation to provide fundamental understanding of these degradation mechanisms and are nowadays well understood. The shift to a dual-layer gate stack also had a profound impact on the time dependent dielectric breakdown (TDDB) introducing a strong polarity dependence in the model parameter. As device scaling continues, stochastic modeling of variability, both at time zero and post stress due to BTI, becomes critical especially for SRAM circuit aging. As we migrate towards novel device architectures like bulk FinFET, SOI FinFETs, FDSOI and gate-all-around devices, impact of self-heating needs to be accounted for in reliability testing.In this paper we summarize the fundamentals of MG/HK reliability and discuss the reliability and characterization challenges related to the scaling of future CMOS technologies.

HfO2 high-k solid-state incandescent devices: performance improvement using a Ti-embedded layer and observation of conductive paths as light-emitting sources

Solid-state incandescent light-emission devices (SSI-LEDs) with a metal-oxide-semiconductor structure are promising candidates for future broadband light-emission devices. In this work, the electrical and light-emission features of SSI-LEDs based on HfO2 high-k thin films with or without the Ti-embedded layer on p-type silicon wafers have been studied. It turns out that the Ti-embedded layer can effectively reduce the turn-on voltage, thus improving the fluorescence efficiency of SSI-LEDs. The combination of scanning electron microscopy, atomic force microscope (AFM) and conductive AFM results unambiguously clarifies that conductive filaments, which are formed due to local thermal excitation during the forming process, are accompanied by the formation of pits on the HfO2 surface and are responsible for the light emission. This work develops an effective approach to improving the luminescence performance of SSI-LEDs and experimentally explains the light-emitting mechanism of such devices, which is of great importance to eventually realizng broadband light-emitting devices with low power consumption.

Improvement in top-gate MoS2 transistor performance due to high quality backside Al2O3 layer

A high quality Al2O3 layer is developed to achieve high performance in top-gate MoS2 transistors. Compared with top-gate MoS2 field effect transistors on a SiO2 layer, the intrinsic mobility and subthreshold slope were greatly improved in high-k backside layer devices. A forming gas anneal is found to enhance device performance due to a reduction in the charge trap density of the backside dielectric. The major improvements in device performance are ascribed to the forming gas anneal and the high-k dielectric screening effect of the backside Al2O3 layer. Top-gate devices built upon these stacks exhibit a near-ideal subthreshold slope of ∼69 mV/dec and a high Y-Function extracted intrinsic carrier mobility (μo) of 145 cm2/V·s, indicating a positive influence on top-gate device performance even without any backside bias.

(Invited) VLSI-CMOS Device Technology Scaling Landscape Based on Fully-Depleted SOI and 3D-FinFET Technologies for the Internet of Everything Era

System- and process-level innovations based on VLSI-CMOS technologies are the drivers to continue Moore’s Law. Especially in the last decade an ever-increasing component integration on SoC’s has driven cost scaling and will continue to do so while approaching the IoT and wearable device area. To keep pace with the manufacturing cost per device scaling an acceleration of new processing methods, concepts and materials has been introduced, such as local strained Si, high-k metal gate, ultra-low-k, 3D FinFET and FDSOI devices. New integration techniques like double and quadruple patterning are needed since EUV lithography cannot be easy introduced in high volume manufacturing. The inflection on the cost per gate trend can be intercepted by differentiated technologies that serve markets for the respective applications such as 22nm and 12nm FDSOI. Those technologies offer a wide variety and individualism for designs to serve the IoT/E era perfectly. SoC innovations need to focus on 3D multi-die package integrations on system level.

Influence of Oxide Interlayer by TiN Metal Gate in High-k First CMOS Devices

Due to its good film stability and electric property of high effective work function, TiN film has been widely used as high-k gate dielectric capping layer or work function metal in advanced High-k/metal gate CMOS devices. In this work, different TiN films were prepared by atomic layer deposition (ALD) and plasma vapor deposition (PVD) respectively, their thermal stability and interaction with gate stack films were investigated. Furthermore, their impacts on interface properties of interfacial oxide/high-k and interfacial oxide/silicon were also studied. The results show that both ALD and PVD TiN films have good thermal stability, while they tend to gather oxygen from atmosphere during sequential process steps. After high temperature annealing, the gathered oxygen in TiN film is easy to diffuse upward into TiN/poly-Si interface to form a thin TiSixOy layer above TiN film, and diffuse downward through high-k dielectric film resulting in interfacial oxide layer (IL) regrowth.

Capacitance-voltage characteristics measured through pulse technique on high-k dielectric MOS devices

Capacitance-voltage (CV) characteristics were investigated for MOS devices with ZrO2 and HfO2 high-k dielectrics using pulse technique and LCR meter. Opposite relative positions of the forward and reverse traces were observed for the CV curves extracted from the two techniques. This unusual phenomenon was believed to be caused by the interface dipoles formed at high-k/SiOx interface, since it was difficult to be convincingly explained by trapping/de-trapping of charges. The effect of interface dipoles on CV characteristics was found to be sensitive to the voltage ramp rate. In addition, a hump in the inversion region for the forward trace in pulse technique was detected. This may be due to an additional current due to the PN junction formed between the substrate and inversion layer via the pulse technique process.

(Invited) A Complete Suite of Experimental Techniques for Electrical Characterization of Conventional and Incoming High-k Dielectric-Based Devices

High permittivity (high-k) dielectric films are of considerable interest as gate oxide materials in advanced complementary metal-oxide-semiconductor (CMOS), in metal-insulator-metal capacitors (MIM), and in dynamic and resistive random access memory devices as well. These materials need to be characterized and qualified prior to their inclusion on massive fabrication processes. In this work we review the standard and new electrical characterization techniques available in our laboratory for the electrical characterization of thin high-k layer-based metal-insulator-semiconductor (MIS) and metal-insulator-metal structures. All of them constitute a complete suite of experimental techniques to carry out an in-depth study of conventional and incoming high-k based devices.

(Invited) A Complete Suite of Experimental Techniques for Electrical Characterization of Conventional and Incoming High-k Dielectric-Based Devices

High permittivity (high-k) dielectric films are of considerable interest as gate oxide materials in advanced complementary metal-oxide-semiconductor (CMOS) [1] as well as in dynamic and resistive random access memory devices (DRAM and ReRAM) [2]. While high-k materials can help to solve gate leakage problems with leading-edge processes, there still are some remaining challenges [3]. Drastic improvements in the quality of high-k films with respect to film density, thermal and electrical stability, quality of the interfaces with silicon substrate and/or metal gates, have been produced. However, there are several technical hurdles such as threshold voltage instabilities, carrier channel mobility degradation, and long-term device reliability. In fact, the performance of high-k film-based CMOS devices is strongly limited by the trapping and detrapping of charges in the pre-existing traps inside the high-k dielectrics [4]; also, reliability and variability are major concerns in the ReRAM development [5, 6]. During the last years, and nowadays, there has been an intense worldwide scientific and technological interest in the area of metal/oxide and oxide/semiconductor interfaces. Defects existing in these emerging materials play an important role in device operation, so their use in nano-semiconductor technology can be seriously endangered. Despite the great effort carried out in the last years, the nature and formation of these defects are not well known yet, so the study of defects is a primary concern to be able to apply techniques which can minimize them. Since electrically active defects are atomic configurations which give rise to electronic sates, developing an atomic-scale understanding of defects is mandatory. Another topic of great interest is the current mechanism observed on high-k materials. The correlation between conduction mechanisms, defect location, and preferential energy values provides very relevant information about the very nature of defects and how these defects could be removed or diminished. In this work we show the application of the standard techniques, as well as the new ones, which we have developed, for the electrical characterization of thin high-k layer-based metal-insulator-semiconductor (MIS) and metal-insulator-metal (MIM) structures. All of them constitute a complete suite of experimental techniques to carry out an in-depth study of conventional and incoming high-k based devices. In Fig. 1 a schematic of the electrical characterization of CMOS devices is shown. As an illustration, Figs. 2(a) and (b) show some results of electrical characterization of MIM structures for ReRAM devices. A whole discussion of the use of these techniques will be given during the conference. [1] D. Panda, and T.-Y. Tseng, Thin Solid Films 531, 1 (2013). [2] J. A. Kittl, K. Opsomer, M. Popovici, N. Menou, et al. Microel. Engin. 86, 1789 (2009). [3] J.-S. Jung, S.-K. Lee, C.-S. Hong, J.-H. Shin, J.-M. Kim, and J.-G. Kang, Thin Solid Films 589, 831 (2015). [4] S. Duenas, H. Castán, H. García, and L. Bailón, in Dielectric Materials, M. A. Silaghi, ed. InTech, ISBN: 978-953-51-0764-4, pp. 213-250 (2012). [5] J. Park, S. Jung, W. Lee, S. Kim, J. Shin, D. Lee, J. Woo, and H. Hwang, IEEE Electron Device Lett. 33, 646 (2012) [6] A. Fantini, L. Goux, R. Degraeve, D. J. Wouters, N. Raghavan, G. Kar, A. Belmonte, Y.Y. Chen, B. Govoreanu, and M. Jurczak, in Proc. IMW, pp. 30-33 (2013). Figure 1

Low-Power High-Density STT MRAMs on a 3-D Vertical Silicon Nanowire Platform

In recent years, researchers have focused toward reduction in power dissipation and cell size to employ spin-transfer torque (STT) magnetic random-access memories (MRAMs) for embedded applications. Hence, the magnetic tunnel junctions (MTJs) with an optimized structure and magnetic properties are being explored to reduce the switching current. However, the switching current reduction in the MTJs generally lowers the data-retention capability. Hence, a different approach to reduce power dissipation using a novel select device should be considered. This paper, therefore, explores the STT MRAM with vertical silicon nanowire gate all around (GAA) high-k select device for superior performance. The MTJ is stacked above the vertical GAA device, so that both occupy the same footprint area to achieve high array density. Furthermore, enhancement of current drive using high-k gate dielectric and its impact on the STT MRAMs are analyzed at different feature sizes. The proposed STT MRAM cell with high-k dielectric (HfO <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> ) lowers the power dissipation by 8%-25% and increases the write margins (WMs) up to 38%, with negligible increment in delay in comparison with the GAA device using low-k dielectric (SiO <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> ). Moreover, asymmetricity is introduced in device configuration to achieve power savings of 25%-30% at high V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">DD</sub> . The proposed asymmetric high-k cell offers a substantially larger tradeoff window between high WMs and low power dissipation.

Temperature Effects on Charge Storage and Transfer of Nanocrystalline CdSe Embedded Zr-Doped HfO2 MOS Memory Device

The influence of temperature on the charge storage and transfer characteristics of the nanocrystalline CdSe embedded Zr-doped HfO2 high-k dielectric on the p-type Si wafer has been studied. With the increase of temperature, the hole-trapping capacity is increased but the electron-trapping follows the opposite trend, which results in a small reduction of the memory window. From the frequency dispersion measurement result, at high temperatures, holes are loosely trapped at the nanocrystal/high-k interface and electrons are mainly trapped in the bulk nanocrystal. The high temperature induces a larger leakage current because it enhances the charge supply and transfer in the high-k stack. At the low applied voltage, the charge transfer follows the Schottky emission mechanism. In the high, positive gate voltage region, charges are transferred following the Poole-Frenkel mechanism at the low temperature and the Fowler-Nordheim mechanism at the high temperature. The temperature has little effect on the sample's leakage current-gate voltage hysteresis due to the large charge trapping capability. In summary, temperature is an important factor in the operation of the nanocrystals embedded high-k memory device because it affects the charge storage and transfer mechanisms.

HfO2 gate dielectric on Ge (1 1 1) with ultrathin nitride interfacial layer formed by rapid thermal NH3 treatment

Interfacial properties of the ALD deposited HfO2 over the surface nitrided germanium substrate have been studied. The formation of GeON (∼1.7nm) was confirmed by X-ray photoelectron spectroscopy (XPS) and high resolution transmission electron spectroscopy (HRTEM) over the germanium surface. The effect of post deposition annealing temperature was investigated to study the interfacial and electrical properties of hafnium oxide/germanium oxynitride gate stacks. The high-k MOS devices with ultrathin GeON layer shows the good electrical characteristics including higher k value ∼18, smaller equivalent oxide thickness (EOT) around 1.5nm and smaller hysteresis value less than 170mV. The Qeff and Dit values are somewhat greater due to the (111) orientation of the germanium and may be due to the presence of nitrogen at the interface. The Fowler–Northeim (FN) tunneling of Ge MOS devices has been studied. The barrier height ΦB extracted from the plot is ∼1eV.

Impact of different NBTI defect components on sub-threshold operation of high-k p-MOSFET

A study of the NBTI reliability of high-k p-MOSFET device for application in subthreshold operation based on different defect mechanism is presented. The impact of the different defect mechanism is studied based on modelling the sub-threshold operation using Two-Stage NBTI model and NBTI-induced positive charges based on energy profiling approach. The time exponent of 0.1 is observed in sub-threshold operation modelled based on the Two-Stage NBTI model while time exponent of 0.3 is observed in sub-threshold operation modelled based energy profiling approach. Considerable threshold voltage shifts are observed during sub-threshold operation based on both defect mechanisms. Extraction of E'centres and E’/Pb H Complex as well as positive charges was found to be temperature dependence hence the degradation is also thermally activated during subthreshold operation for both defect mechanisms.

High-k gate dielectric GaAs MOS device with LaON as interlayer and NH3-plasma surface pretreatment**Project supported by the National Natural Science Foundation of China (Grant Nos. 61176100 and 61274112).

High-k gate dielectric HfTiON GaAs metal-oxide–semiconductor (MOS) capacitors with LaON as interfacial passivation layer (IPL) and NH3- or N2-plasma surface pretreatment are fabricated, and their interfacial and electrical properties are investigated and compared with their counterparts that have neither LaON IPL nor surface treatment. It is found that good interface quality and excellent electrical properties can be achieved for a NH3-plasma pretreated GaAs MOS device with a stacked gate dielectric of HfTiON/LaON. These improvements should be ascribed to the fact that the NH3-plasma can provide H atoms and NH radicals that can effectively remove defective Ga/As oxides. In addition, LaON IPL can further block oxygen atoms from being in-diffused, and Ga and As atoms from being out-diffused from the substrate to the high-k dielectric. This greatly suppresses the formation of Ga/As native oxides and gives rise to an excellent high-k/GaAs interface.