AbstractPLL's (phase‐locked loops) are playing widely important roles in various fields of communication. In recent years, efforts have been shifted toward implementation of the PLL's by means of digital circuits. There arise various problems which are common to that approach, such as the contradictory relation between the phase‐locking range and the jitter suppression, as well as the steady‐state phase error due to the frequency offset.This paper attempts to cope with those problems by improving the conventional binary quantized phase comparator which produces only +1 and ‐1 outputs. A new phase‐frequency comparator is proposed which adaptively modifies the phase comparison characteristics according to the frequency error and the input phase jitter, aiming at an improvement of DPLL performance.The modified comparator improves performance of the loop by increasing its output gain in the pull‐in state, and decreasing the gain in the steady state. When there exists a frequency offset, the cycle slip and the steady‐state phase error are detected, and the output frequency is controlled by adding a constant quantity which reduces the frequency error to the comparator output in the steady state.By this scheme, the locking range is increased. Theoretical analyses are made for the frequency acquisition, phase acquisition and jitter suppression for the proposed loop. The result of the theoretical calculation is compared with the result of simulation, and it is verified that the proposed loop structure offers a wide locking range and a high jitter suppression, at the same time improving the steady‐state phase error.