High Ge Content SiGe Research Articles

An Assessment of the Lateral Selective Etching, with HCl, of High Versus Low Ge Content SiGe Layers

We have evaluated the feasibility of selectively etching, with gaseous HCl, high versus low Ge content SiGe layers. To that end, we have grown {20 to 25 nm thick Si / ~ 12-15 nm thick Si0.8Ge0.2 or Si0.75Ge0.25 / ~ 11-14 nm thick Si0.5Ge0.5} multilayers on SOI substrates. After a low temperature capping with SiN, such stacks were patterned into regular arrays of square mesas or lines with a stop on the buried oxide, to laterally etch the layers of interest. We first determined, at 500°C, 600 Torr, the (001) blanket HCl etch rates of SiGe 30% and 40%: 1.4 and 5.3 nm min.-1. We then switched over to patterned wafers. The lateral selective etching of Si0.5Ge0.5 versus Si0.8Ge0.2 (and Si) was feasible and the following features highlighted: (i) Si0.5Ge0.5 lateral etch rates along the <110> directions were much smaller than in the vertical [001] direction and (ii) because of micro-loading, lateral etch rates were definitely higher for squares than for lines (0.9-1.1 nm min.-1 for lines, to be compared with 1.7–2.1 nm min.-1 for squares). Meanwhile, the lateral selective etching of Si0.5Ge0.5 versus Si0.75Ge0.25 was far from being perfect, with much higher Si0.5Ge0.5 etch rates and a significant Si0.75Ge0.25 recessing at tunnel entrances. Si0.75Ge0.25 floors and ceilings were otherwise far more etched and thus tilted than Si0.8Ge0.2 ones. Inserting very thin Si spacers between Si0.5Ge0.5 cores and Si0.75Ge0.25 claddings partly solved those issues, with no recessing and lesser etchings at the entry points of tunnels.

Increasing the critical thickness of SiGe layers on Si substrates using sputter epitaxy method

SiGe layers were formed on Si substrates by using the sputter epitaxy method. The growth temperatures were 400 and 560 °C, and the growth rates of the SiGe layers were about 2.7–5.4 nm/min, depending on the Ge composition ratio. The samples formed by gas-source molecular beam epitaxy (GSMBE) were also fabricated for comparison. The lattice-mismatch ratio was investigated using X-ray diffraction, the surface roughness was observed by an atomic force microscope, and the crystallinity of the SiGe layers was observed by a transmission electron microscope. The critical thickness of the SiGe layers was estimated from the lattice-mismatch ratio, and the critical thickness at a growth temperature of 400 °C was higher than that in the GSMBE and previous reports. The surface roughness of the Si1-xGex layers (x = 0.24–0.51) with no strain relaxation was flat and below 1 nm. Without any buffer techniques, high Ge content SiGe layers with no strain relaxation were directly formed on Si substrates using the sputter epitaxy method. It is considered that the sputter epitaxy method can grow SiGe layers at relatively low temperatures and can increase the critical thickness.

Dopant Redistribution and Activation in Ga Ion-Implanted High Ge Content SiGe by Explosive Crystallization during UV Nanosecond Pulsed Laser Annealing

Explosive crystallization (EC) is often observed when using nanosecond-pulsed melt laser annealing (MLA) in amorphous silicon (Si) and germanium (Ge). The solidification velocity in EC is so fast that a diffusion-less crystallization can be expected. In the contacts of advanced transistors, the active level at the metal/semiconductor Schottky interface must be very high to achieve a sub-10−9 ohm·cm2 contact resistivity, which has been already demonstrated by using the dopant surface segregation induced by MLA. However, the beneficial layer of a few nanometers at the surface may be easily consumed during subsequent contact cleaning and metallization. EC helps to address such kind of process integration issues, enabling the optimal positioning of the peak of the dopant chemical profile. However, there is a lack of experimental studies of EC in heavily-doped semiconductor materials. Furthermore, to the best of our knowledge, dopant activation by EC has never been experimentally reported. In this paper, we present dopant redistribution and activation by an EC process induced by UV nanosecond-pulsed MLA in heavily gallium (Ga) ion-implanted high Ge content SiGe. Based on the obtained results, we also highlight potential issues of integrating EC into real device fabrication processes and discuss how to manage them.

Multilayered highly-active dopant distribution by UV nanosecond melt laser annealing in Ga and B co-implanted high Ge content SiGe:B epilayers

Advanced transistors strongly require access resistance reduction, and the most dominant factor in parasitic resistance components is contact resistance at the metal/semiconductor interface. This is more challenging in p-type contacts, where increasing Ge content in SiGe contact epilayers results in quite low solubility of boron. Melt laser annealing (MLA) is known as a way of surpassing such solubility limit owing to metastable dopant incorporation into semiconductor materials. In this study, we combine MLA with co-implantation of boron and gallium into high Ge content SiGe:B epilayers to realize multilayered highly-active dopant distribution which should be more favorable for process integration.

Formation mechanism of high Ge content SiGe epilayer on Si by liquid phase epitaxy using Ge-Sn solution

High germanium (Ge) content silicon germanium (Si1−xGex) epilayers with the composition x over 0.9 were prepared on Si(111) substrate by liquid phase epitaxy (LPE). As known, a lattice mismatch high to the degree of 4.2% between Ge and Si has made the direct growth of high Ge content Si1−xGex on Si substrate quite challenging for LPE. However, self-organized Si1−xGex films grown with a grading composition were recognized by cross-sectional scanning electron microscopy/energy dispersive spectroscopy (SEM/EDS). The film structure obtained could be further divided into three layers according to the distribution variation of elemental composition. The initial Si1−xGex layer showed a tardy grading in the Ge composition from 0.1 to 0.15 within a thickness of 21 - 33 μm. Then, the second layer was featured by an abrupt crossover to Ge-rich condition in the composition distribution within a thickness of about 8 - 12 μm. Finally, the top Si1−xGex layer demonstrated a consistently high Ge content (x > 0.9) within a thickness of 2 – 4 μm.It is found that using a Ge-Sn initial growth solution, commencing the LPE at 950 °C, and terminating the growth at an appropriate temperature suggested by the Ge-Sn phase diagram present a feasible methodology to prepare high Ge content SiGe epilayer on Si(111) substrate. In this work, we focus on exploring the formation mechanism of high Ge content SiGe epilayer on Si by LPE by combining the SEM/EDS analysis results with both Si-Sn and Ge-Sn phase diagrams.

Surface segregated Ga, In, and Al activation in high Ge content SiGe during UV melt laser induced non-equilibrium solidification

The impact of solidification front velocity (SFV) on dopant segregation and activation surpassing the equilibrium solid solubility limit was investigated in high Ge content SiGe using UV nanosecond melt laser annealing (MLA). We first simulated the SFV evolution in the MLA-induced solidification of a SiGe binary system. It was then combined with the near-surface atomic and electrically active dopant concentrations measured in the Ga, In, and Al-implanted SiGe after MLA. Solute trapping phenomenon and self-compensation effect of the dopants were discussed to capture a part of their segregation and activation dynamics in the presented SiGeX ternary systems.

Segregation and activation of Ga in high Ge content SiGe by UV melt laser anneal

The feasibility of dopant activation surpassing the equilibrium solid solubility limit by using an out of equilibrium melt laser annealing (MLA) process was investigated. To that end, we used an UV excimer nanosecond laser annealing and studied the segregation and activation of dopants in a Ga-implanted SiGe 50% epilayer. Dopant segregation is of great interest for future nodes to further improve contact resistivity in transistors. However, there is a lack of in-depth study about their activation. In this paper, we first reported very high Ga activation well above the equilibrium solid solubility limit when the partial Si0.5Ge0.5:Ga melt regime was assessed. The dopant segregation phenomenon, together with the surface morphology change of the Si0.5Ge0.5:Ga epilayer, was then induced by MLA. A very clear honeycomblike surface pattern was observed in the full Si0.5Ge0.5:Ga melt regime, while it was less pronounced in the partial melt regime. This honeycomblike pattern would be the result of dopant precipitation at the liquid–solid interface during solidification. Our simulation results highlighted that solidification velocity could play a key role in the substitutional incorporation of Ga atoms in a SiGe lattice.

(Invited) Advanced Replacement High-K/Metal Gate Stack Engineering for High-Performance Strained Silicon-Germanium Finfets with High Ge Content

Strain engineering for pFETs has been conventionally enabled utilizing embedded SiGe in the source/drain regions to continuously boost the transistor current drive and transconductance [1]. Historically, for planar technologies, transconductance was monotonically improved by advancing the technology generations. However, this trend for transconductance, when properly normalized to the effective device width (fin perimeter) is no longer observed when FinFETs were introduced to the mainstream CMOS to improve the short channel effects for sub 30nm gate lengths [2]. The FinFET transconductance saturation or drop be attributed to ineffectiveness of the embedded SiGe stressors (in spite of higher mobility near-(110) surfaces) and/or increased contribution of the S/D resistance as the contacted gate pitch size aggressively scales down. Unless there is a strong and reliable method to externally apply gigantic strain to the Si fin channel, using strained SiGe (s-SiGe) channel, with built-in uniaxial compression, is a strong option to overcome this issue. In fact, SiGe has been utilized in CMOS industry as a knob to control the threshold voltage (Vth) and in part to boost the pFET reliability and transport [3]. Moreover, introduction of SiGe channel for planar pFET has improved reliability, resulting in further Capacitance-Equivalent-oxide-Thickness (CET) scaling over Si. For s-Si1-xGex FinFETs, choice of Ge content (x) is not trivial. Adding more Ge can ideally build in more channel stress resulting increased hole mobility and current drive. However, epitaxial-defect-driven fin height control due to the critical thickness constraints, process thermal budget, bandgap reduction and gate-induced drain leakage (GIDL) control remain challenging. In particular, High-Ge-Content (HGC) s-SiGe FinFETs are of great interest for two reasons, from the transport point of view: First, very high level of strain (close to 3GPa) can be achieved when lattice matched to Si [4]. Second, if strain-relaxed buffer (SRB) SiGe with moderate Ge % is used to tensily strain Si nFET, higher Ge is required to compressively strain the pFET [5]. The GIDL issue can be mitigated by operating the high-performance (HP) device at a lower VDD, i.e. below 0.6V, in line with logic roadmap [4]. Controlling the HFIN, to be competitive with the state-of-the-art Si FinFETs, remains challenging. Above all, a major challenge is associated with the gate stack and interface trap control which is more pronounced in HGC SiGe than Si and pure Ge. In this talk, key process details to enable relatively tall fins and optimized replacement high-k metal gate (RMG) stacks in high-Ge-content SiGe will be discussed and their impact on key device characteristics will be presented. In particular, we review our recent advancement to achieve optimized RMG IL and passivation [6], high hole mobility and record performing short channel pMOS FinFETs. In additions, a metal gate work-function tuning solution will be presented utilizing an ultra-thin replacement metal-gate scheme to achieve target high-performance off current down to 15nm gate lengths.

Prospects of High-Ge-Content Strained SiGe for Advanced FinFET Generations

High mobility materials such as strained Si1-xGexor III-V are promising channel candidates for advanced FinFET generations. By incorporation of moderate Ge content (x~0.2-0.3) into the channel of FinFETs, we have demonstrated pMOSFETs with superior extrinsic and intrinsic electrical characteristics suitable for 10nm technology generations and beyond [1]. To further boost pMOS FinFET performance, High-Ge-Content (HGC) SiGe FETs have recently drawn significant attention due to their enhanced transport and reliability properties and compatibility with bulk or SOI substrates [2, 3]. In addition, compared to strained pure germanium, they can offer reduced off-state tunneling leakage due to their relatively larger bandgap [4]. It has been observed that with high-Ge content around x~0.7, superior hole mobility values are achievable for planar biaxial strained SiGe on relaxed buffer layers and the mobility sensitivity to the strain level from underlying relaxed buffer is small when the buffer Ge content is above 30% [5]. Thus, HGC SiGe is an attractive pFET candidate especially when considered as a counterpart for nFET with s-Si FinFET technology [6], where higher Ge content is indeed required to compensate the built-in tension of s-Si. Utilization of HGC SiGe in a FinFET architecture by direct epitaxial growth is quite challenging due to very low (sub-10nm) epitaxial critical thickness constraints, resulting in high levels of defectivity which may be detrimental to the device functionality. In advanced FinFET technologies, relatively tall fins in tight pitches are required to increase the current per foot print and this may be quite challenging for high-Ge content strained SiGe FinFETs. Alternate approaches such as enhanced 3D Ge condensation [3] may be considered to mitigate the aforementioned issue. On the other hand, gate stack and interface passivation of SiGe with mid to high Ge range is more challenging than pure Si or pure Ge channel MOSFETs. While traditionally Si cap has been used to passivate the SiGe MOSFETs, this approach may not be optimal for scaled nodes where scaled EOT is required for electrostatics integrity of the transistors. Most devices fabricated using a Si-cap-free approach exhibit high levels of interface trap densities leading to mobility degradation and increased sub-threshold leakage. Moreover, enhance trap assisted tunneling can happen in the off state for high-Ge content SiGe due to its lower bandgap. In this talk, we review IBM's recent research activities on HGC SiGe FinFETs with Ge content over 50%. In particular, gate stack, passivation and EOT scaling are major factors in achieving high quality devices based on HGC SiGe. We present our results based on a Si-cap-free surface passivation combined with aggressive EOT scaling down to sub-7Å to achieve acceptable sub-threshold swings for both gate first and replacement high-K/metal gate FinFET integration flows. The width dependence of hole mobility for various device sizes from very wide (planar) to ultra-narrow (scaled FinFETs) would be presented and discussed in detail. In addition, various short channel device aspects such as impact of S/D junction process on performance and electrostatics, off-state leakage current, transconductance and current drive would be discussed. We conclude that high-Ge content SiGe FinFETs are suitable candidates for advanced high-performance logic FinFET applications, especially at low operating voltages (VDD), while their suitability for low or ultra-low power applications is questionable.

Prospects of High-Ge-Content Strained SiGe for Advanced FinFET Generations

High Ge content SiGe FETs have recently drawn significant attention as a candidate for p-MOSFETs due to their enhanced transport and reliability properties and compatibility with bulk or SOI substrates. In addition, compared to strained pure germanium, they can offer reduced off-state tunneling leakage due to their relatively larger bandgap. Utilization of high Ge content SiGe in a FinFET architecture by direct epitaxial growth is quite challenging due to epitaxial critical thickness constraints, resulting in high levels of defectivity which may be detrimental to the device functionality and performance. In this paper, we review our recent progress on high Ge content SiGe FinFETs with Ge content over 60%. In particular, gate stack, passivation and equivalent oxide thickness scaling are major factors in achieving high quality devices based on high Ge content SiGe. We present our results based on a Si-cap-free FinFET surface passivation to achieve excellent sub-threshold swings for both gate first and replacement high-K and metal gate integration flows. In addition, various device aspects such as transport and mobility, S/D and junction, off-state drain leakage current and short channel performance are discussed.

(Invited) Strained SiGe on Insulator FinFETs: a P-FET Candidate for 10nm Node

Performance enhancement using conventional stress elements such as stress liners or embedded source/drain is significantly decreased at extremely tight gate pitch, required for 10nm node and beyond [1]. This issue is more pronounced for non-planar architectures such as FinFETs, especially those made on SOI substrates. For p-type MOSFETs, SiGe is a great candidate due to its intrinsic lower effective mass and better transport properties than Si. SiGe has been utilized in CMOS industry for IBM SOI 32nm and 22nm generations, as a knob to adjust the PFET threshold voltage and performance enhancement [2, 3]. However, it is shown that SiGe with moderate Ge content and no strain does not provide noticeable short-channel benefit over Si and as a result, strain plays a significant role in high-performance SiGe channel pFETs [4]. While higher Ge content SiGe materials can offer lower effective mass and have potential for better transport properties [5], their reduced bandgap by increasing Ge content brings concern for some CMOS applications. This results in increased gate-induced drain leakage and high off current due to increased band-to-band or trap-assisted tunneling [6]. Moreover, the interface passivation for higher Ge content SiGe is extremely challenging resulting in significant sub-threshold leakage and degraded low field mobility. The direct consequence is the degraded short channel on-state current at the target off-current at a scaled VDD. It has been shown that by patterning of biaxially strained SiGe layers, strain can be transformed to asymmetric strain [7, 8] where the effective mass is significantly lowered and higher hole velocities can be achieved [5]. Therefore, the strain state in a scaled fin fabricated from biaxially strained substrates is pure uniaxial with optimal benefit for hole transport. The combination of uniaxial strain with great electrostatic integrity due to the non-planar device architecture as well as more manufacturing-friendly process, makes the moderate Ge content (such x=0.2-0.3) SiGe a very promising candidate for future generation of FinFETs. In order to evaluate the performance of s-SiGe FinFETs, SGOI substrates were fabricated using Ge condensation technique. This process is SOI CMOS compatible, where SiGe can be locally condensed in the pFET region while Si can be used for nFET or other on-chip applications. A final Ge fraction of x = 27.5% was measured by XRD, with minimal strain relaxation consistent with SIMS results (Figure 1(a)). The defectivity of SGOI substrates was measured using ex-situ Si capping followed by SECCO etch and dislocation density of ~ 1e4 cm-2 was measured for an optimized epitaxy and Ge condensation process. A gate first process flow was developed to fabricate our SiGe pMOS FinFETs [9]. As s-SiGe reactive-ion-etch resistance is much less than that of Si, the spacer RIE process was optimized to minimize fin recess in S/D regions and thus minimize stress relaxation. Raised S/D regions were formed using an ion-implant-free process by in-situ Boron-doped (ISBD) Si1-yGey (y > 40%) epitaxy with high Boron concentration, and dopant drive-in under the spacer to form the extensions. SGOI fins with vertical sidewalls and widths as scaled as 10nm demonstrated. Figure 1(b) shows typical XTEM of s-SiGe PMOS FinFET with sub-20nm physical gate length.Typical transfer and output characteristics of single-fin SiGe-channel PFETs (Fig. 2) exhibit excellent electrostatics with DIBL~50mV/V and SS ~90 mV/decade. In spite of high REXT ~ 0.4kΩ.μm, ION = 1.1 mA/µm was obtained at IOFF = 100 nA/µm and VDD = 1V. This high on current is attributed to the high source injection velocity exceeding 1e7 cm/s which is higher than SOI FinFETs with no stressors [10], and also higher than state-of the art bulk FinFETs [11]. Moreover, the SiGe PMOS FinFETs offers low off-state leakage suitable for high-performance and low-power applications. These criteria are hard to meet using state of the art Ge pFETs due to the significantly smaller bandgap [12]. In addition, unlike state of the art Ge pFETs, using a metal gate with a mid-gap work-function, target Vth has been achieved. In conclusion, we have demonstrated that s-SiGe channel FinFETs are a promising pFET candidate for future generations of high-performance devices and have a more manufacturable friendly process, than high-Ge content SiGe or Ge.REFERENCES[1] W. Haensch, IBM J. Res. & Dev., 2006. [2] S. Krishnan, IEDM 2011. [3] C. Ortolland, IEDM 2013. [4] A. Khakifirooz, IEEE TED 2009. [5] L. Gomez, IEEE TED, 2009. [6] C. Ni Chleirigh, IEEE TED, 2008. [7] T. Irisawa, IEDM 2005. [8] P. Hashemi, APL 2007. [9] P. Hashemi, VLSI 2013. [10] T. Yamashita, VLSI 2011. [11] C. Auth, VLSI 2012. [12] B. Duriez, IEDM 2013.

(Invited) High Ge Content SiGe Thin Films: Growth, Properties and Integration

Although SiGe with low Ge content was used in BiCMOS devices for a relatively long time, its integration in pMOS transistors at 90 nm technological node opened for SiGe totally new horizons. During the course of years Ge content in SiGe gradually increased, as well as its influence. Nowadays, practically every pMOS transistor is using SiGe either as a strain booster in the case of high performance pMOS or as a SiGe channel allowing Vt correction of low power pMOS transistors. Integration of high mobility materials (SiGe, Ge) in the fin FET fashion seem to be rather logical step in order to move to the next 10 nm technological node and beyond.In this contribution we will first discuss the growth of SiGe with high Ge content with different precursors like silane, disilane, germane and digermane (Fig. 1). Next we will elaborate on relaxation of SiGe thin films (plastic and elastic (Fig. 2)) and SiGe processes selectivity. Finally we will present the integration of high Ge content SiGe in different types of pMOS transistors: Si FinFETs, strained SiGe core FinFETs, strained SiGe cladding FETs and strained Ge FETs (Fig. 3). Challenges and possible solutions for different pMOS approaches listed above will be put forward. Acknowledgements The imec core CMOS program members, European commission, local authorities and imec pilot line are acknowledged for their support. Fig.1 Ge concentration of SiGe grown with different precursors at different temperatures. Fig.2 An example of elastic relaxation of SiGe caused by too high process temperature. Fig.3 Examples of SiGe integration in different device structures. 1) SiGe S/D of Si fin; 2) SiGe core pMOS; 3) SiGe cladding pMOS. 4) SiGe S/D on rGe pMOS.

(Invited) Application of Selective Epitaxial Growth in the Sub 20 nm FinFET Device Fabrication

Application of high Ge content (up to 70%) SiGe in the fin FET pMOS transistors for the following 14 and 10 nm nodes is suggested and reasoned. Use of Si:C and Si:P for nMOS counterpart is discussed and difficulties of selective epitaxial growth of such layers are evaluated. Merging of fins in source/drain areas is presented and main features are shown.

High Ge Content SiGe Selective Processes for Manufacturing Source/Drain in the Next Generations of pMOS Transistors

Selectivity of different SiGe processes towards oxide and nitride has been studied on both: blanket and patterned Si wafers. Three different precursors: silane, dichlorosilane and disilane were used for SiGe growth. It was found that growth of SiGe with Ge content higher than 35% is intrinsically selective towards SiO2; SiGe with any Ge content, up to pure Ge, could not be grown selectively towards nitride; in order to get selectivity towards nitride an etching gas should be used and its amount in the gas phase decreases with the Ge content increase.

High Ge Content SiGe Selective Processes for Source/Drain in Manufacturing the Next Generations of pMOS Transistors

Selectivity of different SiGe processes toward oxide and nitride has been studied on both: blanket and patterned Si wafers. Three different precursors: silane, dichlorosilane and disilane were used for SiGe growth. It was found that the growth of SiGe with Ge content higher than 35% was intrinsically selective toward SiO2; SiGe with any Ge content, up to pure Ge, could not be grown selectively toward nitride; in order to get selectivity toward nitride, an etching gas should be used and its amount in the gas phase decreases with an increase of the Ge content.

High Ge Content SiGe Selective Processes for Manufacturing Source/Drain in the Next Generations of pMOS Transistors

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Growth of high Ge content SiGe on (110) oriented Si wafers

Growth of high (above 40%) Ge content SiGe by applying silane and dichlorosilane as Si precursors on (110) Si is investigated. In the case of silane based processes Ge concentration is ~20% higher, whereas for dichlorosilane based processes it is ~30% lower on (110) Si compared to (100) Si. The morphology of the grown layers is found to be dependent on Ge concentration, layer thickness and process temperature. Use of optimized deposition parameters and adequate thickness results in high quality strained SiGe layers. Integration of high Ge content SiGe layers in multiple gate filed-effect transistor structures shows the expected differences in Ge content on the different Si planes forming Si fin. These differences can be avoided by adjusting the fin orientation on the Si wafer resulting in equal planes on the fin's top and sidewalls. When the investigated SiGe layers are incorporated in the buried channel field effect transistor structures on (110) Si wafers a significant thickening at the active windows edge is observed. It is speculated that this effect is connected with elastic SiGe relaxation caused by a non optimized process temperature.

HCl Selective Etching of SiGe versus Si in Stacks Grown on (110)

We have investigated the lateral HCl selective etching of SiGe versus Si in various patterned (110) SiGe/Si stacks. Given that Si(110) vertical etch rates are roughly 4 times higher than Si(100) ones, a moderate HCl partial pressure (0.4 Torr) was adopted for this 600-700C study. A definite SiGe versus Si etch selectivity has been demonstrated on (110) for 30-40% of Ge (none for 20% of Ge). SiGe lateral etch rates higher in the [1-10] than in the [001] direction have also been evidenced. A definite increase of both [1-10] and [001] lateral etch rates occurred when increasing the Ge content, the SiGe layer thickness and the etch temperature. Mean selectivities for 15 nm thick layers were however not that high, 20 for Si0.7Ge0.3 and 60 for Si0.6Ge0.4. [1-10] versus [001] etch anisotropy was otherwise minimized for low temperature etches, high Ge content and thick SiGe layers.

Strain relaxation in high Ge content SiGe layers deposited on Si

We have used Raman spectroscopy, transmission electron microscopy, x-ray diffraction, and x-ray photoemission spectroscopy to investigate strain relaxation mechanism of Si0.22Ge0.78 heteroepitaxial layer deposited on Si substrates in tensile, neutral, and compressive strain conditions. The three regimes have been obtained by interposing between the SiGe layer and the substrate a fully relaxed Ge layer, a partially relaxed Ge layer, or growing directly the alloy on Si. We found that the deposition of a Ge buffer layer prior to the growth of the SiGe is very promising in view of the realization of thin virtual substrates on silicon to be used for the deposition of strain-controlled high Ge content SiGe alloys. We demonstrate that this is mainly due to the strain relaxation mechanism in the Ge layer occurring via insertion of pure edge 90° misfit dislocations (MDs) and to the confinement of threading arms in to the Ge layer due to a second MD network formed at the SiGe/Ge heterointerface.

Reverse graded relaxed buffers for high Ge content SiGe virtual substrates

An innovative approach is proposed for epitaxial growth of high Ge content, relaxed Si1−xGex buffer layers on a Si(001) substrate. The advantages of the technique are demonstrated by growing such structures via chemical vapor deposition and their characterization. Relaxed Ge is first grown on the substrate followed by the reverse grading approach to reach a final buffer composition of 0.78. The optimized buffer structure is only 2.8μm thick and demonstrates a low surface threading dislocation density of 4×106cm−2, with a surface roughness of 2.6nm. The buffers demonstrate a relaxation of up to 107%.