High Gate Research Articles

The heterointerface characterization of BaF2 or MgF2 on the hydrogenated diamond by X-ray photoelectron spectroscopy

Group-II fluorides (BaF2 and MgF2) insulators are deposited on hydrogenated (C–H) diamonds by E-beam evaporator at room temperature. The bandgaps, chemical bonds and band offsets of fluorides are investigated by the high-resolution X-ray photoelectron spectroscopy (XPS) measurements. The XPS results show bandgap energies of 9.4 ± 0.2 eV for BaF2 and 9.7 ± 0.2 eV for MgF2 by F 1s energy loss spectra. The valence band offsets (ΔEV's) of BaF2/MgF2 on the C–H diamond are determined as 5.2 ± 0.2 and 4.8 ± 0.2 eV, respectively. There are both type II energy band configuration for BaF2 and MgF2 on the C–H diamond with conduction band offsets of 1.3 ± 0.2 eV and 0.6 ± 0.2 eV, respectively. The relatively oxygen-weak or oxygen-free fluoride/C–H diamond interface and large ΔEV suggest that fluorides are an excellent gate dielectric for the C–H diamond field-effect transistors with high hole mobility and low gate leakage.

Efficient simulation of potential energy operators on quantum hardware: a study on sodium iodide (NaI)

This study introduces a conceptually novel polynomial encoding algorithm for simulating potential energy operators encoded in diagonal unitary forms in a quantum computing machine. The current trend in quantum computational chemistry is effective experimentation to achieve high-precision quantum computational advantage. However, high computational gate complexity and fidelity loss are some of the impediments to the realization of this advantage in a real quantum hardware. In this study, we address the challenges of building a diagonal Hamiltonian operator having exponential functional form, and its implementation in the context of the time evolution problem (Hamiltonian simulation and encoding). Potential energy operators when represented in the first quantization form is an example of such types of operators. Through systematic decomposition and construction, we demonstrate the efficacy of the proposed polynomial encoding method in reducing gate complexity from O(2n)\\documentclass[12pt]{minimal} \\usepackage{amsmath} \\usepackage{wasysym} \\usepackage{amsfonts} \\usepackage{amssymb} \\usepackage{amsbsy} \\usepackage{mathrsfs} \\usepackage{upgreek} \\setlength{\\oddsidemargin}{-69pt} \\begin{document}$$\\mathcal {O}(2^n)$$\\end{document} to O∑i=1rnCr\\documentclass[12pt]{minimal} \\usepackage{amsmath} \\usepackage{wasysym} \\usepackage{amsfonts} \\usepackage{amssymb} \\usepackage{amsbsy} \\usepackage{mathrsfs} \\usepackage{upgreek} \\setlength{\\oddsidemargin}{-69pt} \\begin{document}$$\\mathcal {O}\\left( \\sum _{i=1}^{r} {} ^nC_r \\right)$$\\end{document} (for some r≪n\\documentclass[12pt]{minimal} \\usepackage{amsmath} \\usepackage{wasysym} \\usepackage{amsfonts} \\usepackage{amssymb} \\usepackage{amsbsy} \\usepackage{mathrsfs} \\usepackage{upgreek} \\setlength{\\oddsidemargin}{-69pt} \\begin{document}$$r\\ll n$$\\end{document}). This offers a solution with lower complexity in comparison to the conventional Hadamard basis encoding approach. The effectiveness of the proposed algorithm was validated with its implementation in the IBM quantum simulator and IBM quantum hardware. This study demonstrates the proposed approach by taking the example of the potential energy operator of the sodium iodide molecule (NaI) in the first quantization form. The numerical results demonstrate the potential applicability of the proposed method in quantum chemistry problems, while the analytical bound for error analysis and computational gate complexity discussed, throw light on issues regarding its implementation.

Van der Waals Epitaxially Grown Molecular Crystal Dielectric Sb2O3 for 2D Electronics.

Two-dimensional (2D) semiconducting materials have attracted significant interest as promising candidates for channel materials owing to their high mobility and gate tunability at atomic-layer thickness. However, the development of 2D electronics is impeded due to the difficulty in formation of high-quality dielectrics with a clean and nondestructive interface. Here, we report the direct van der Waals epitaxial growth of a molecular crystal dielectric, Sb2O3, on 2D materials by physical vapor deposition. The grown Sb2O3 nanosheets showed epitaxial relations of 0 and 180° with the 2D template, maintaining high crystallinity and an ultrasharp vdW interface with the 2D materials. As a result, the Sb2O3 nanosheets exhibited a high breakdown field of 18.6 MV/cm for 2L Sb2O3 with a thickness of 1.3 nm and a very low leakage current of 2.47 × 10-7 A/cm2 for 3L Sb2O3 with a thickness of 1.96 nm. We also observed two types of grain boundaries (GBs) with misorientation angles of 0 and 60°. The 0°-GB with a well-stitched boundary showed higher electrical and thermal stabilities than those of the 60°-GB with a disordered boundary. Our work demonstrates a method to epitaxially grow molecular crystal dielectrics on 2D materials without causing any damage, a requirement for high-performance 2D electronics.

Near-term distributed quantum computation using mean-field corrections and auxiliary qubits

Distributed quantum computation is often proposed to increase the scalability of quantum hardware, as it reduces cooperative noise and requisite connectivity by sharing quantum information between distant quantum devices. However, such exchange of quantum information itself poses unique engineering challenges, requiring high gate fidelity and costly non-local operations. To mitigate this, we propose near-term distributed quantum computing, focusing on approximate approaches that involve limited information transfer and conservative entanglement production. We first devise an approximate distributed computing scheme for the time evolution of quantum systems split across any combination of classical and quantum devices. Our procedure harnesses mean-field corrections and auxiliary qubits to link two or more devices classically, optimally encoding the auxiliary qubits to both minimize short-time evolution error and extend the approximate scheme’s performance to longer evolution times. We then expand the scheme to include limited quantum information transfer through selective qubit shuffling or teleportation, broadening our method’s applicability and boosting its performance. Finally, we build upon these concepts to produce an approximate circuit-cutting technique for the fragmented pre-training of variational quantum algorithms. To characterize our technique, we introduce a non-linear perturbation theory that discerns the critical role of our mean-field corrections in optimization and may be suitable for analyzing other non-linear quantum techniques. This fragmented pre-training is remarkably successful, reducing algorithmic error by orders of magnitude while requiring fewer iterations.

Terahertz binary computing in a coupled toroidal metasurface

The applications of terahertz metamaterials are being actively explored in recent times for applications in high-speed communication devices, miniature photonic circuits, and bio-chemical devices because of their wide advantages. The toroidal resonance, a new type of metasurface resonance, has been examined with great interest to utilize its properties in terahertz metasurface applications. This study reports a proof of concept design of a toroidal metasurface that experimentally demonstrates binary computing operations in the terahertz frequency regime. The analog computing of binary operations is achieved by the passive tuning of distance between the split ring resonators comprising the meta-molecule. The amplitude modulation is utilized as a method of determining the Boolean logic outputs of the system. The proposed metasurface could be further optimized for high amplitude modulations and active logic gate operations using tunable materials including graphene and ITO. The proposed metasurface consists of three split-ring resonators, and the near-field coupling between the adjacent resonators dictates the Boolean operations. A multipole analysis of the scattered powers of terahertz radiation determines the toroidal excitation in the metasurface. The proposed metasurfaces experimentally define AND Boolean logic operation at 0.89 terahertz, and OR Boolean logic operation at 0.97 terahertz. Numerical simulations support the experimentally obtained results. Additionally, we numerically report the excitation of NAND operation at 0.87 THz. Such toroidal analog computing metasurfaces could find applications in digitized terahertz circuits and integrated photonic devices.

An Enhanced Synaptic Plasticity of Electrolyte-Gated Transistors through the Tungsten Doping of an Oxide Semiconductor

Oxide electrolyte-gated transistors have shown the ability to emulate various synaptic functions, but they still require a high gate voltage to form long-term plasticity. Here, we studied electrolyte-gated transistors based on InOx with tungsten doping (W-InOx). When the tungsten-to-indium ratio increased from 0% to 7.6%, the memory window of the transfer curve increased from 0.2 V to 2 V over a small sweep range of −2 V to 2.5 V. Under 50 pulses with a duty cycle of 2%, the conductance of the transistor increased from 40-fold to 30,000-fold. Furthermore, the W-InOx transistor exhibited improved paired pulse facilitation and successfully passed the Pavlovian test after training. The formation of WO3 within InOx and its ion intercalation into the channel may account for the enhanced synaptic plasticity.

Improved breakdown performance in recessed-gate normally off GaN MIS-HEMTs by regrown fishbone trench

This work develops a regrown fishbone trench (RFT) structure in selective area growth (SAG) technique to fabricate recessed-gate normally off GaN metal–insulator–semiconductor high electron mobility transistors (MIS-HEMTs). The RFT structure effectively modulates the electric field at high drain and gate biases, thus allowing the device to feature improved off-state and gate breakdown performance with a high positive Vth of 2 V. The simulated carrier concentration and electric field distributions reveal the mechanism of electric field weakening by RFT architecture. Meanwhile, the current collapse phenomenon is significantly suppressed, and the gate voltage swing is also enlarged. The maximum gate drive voltage of 9.2 V for 10-year reliability of RFT GaN MIS-HEMT, together with the improved linearity and block voltage, broadens the applications of SAG devices. Furthermore, the RFT structure also provides an etching-free method for fabricating normally off GaN MIS-HEMTs with multi-dimensional gates.

Al-rich AlGaN high electron mobility transistor gate metallization study up to 600 °C in air

Al-rich AlGaN high electron mobility transistor gate metallization study up to 600 °C in air

High speed universal NAND gate based on weakly coupled RF MEMS resonators

High speed universal NAND gate based on weakly coupled RF MEMS resonators

Comprehensive Investigation of Gate Oxide Instability in 4H-SiC MOSFETs and MOS Capacitors Under High Gate Bias Stress

Comprehensive Investigation of Gate Oxide Instability in 4H-SiC MOSFETs and MOS Capacitors Under High Gate Bias Stress

Output breakdown characteristics of amorphous InGaZnO thin-film transistors at high gate voltage

Output characteristics of top-gate amorphous InGaZnO thin-film transistors are investigated at high gate voltage. With the increasing drain voltage, an output breakdown crops up closely following a drastic uprush of drain current. Such dramatically elevated drain current derives from the self-heating (SH) effect-generated channel donors. Measured at different high gate voltages, the output breakdown occurs in either linear or saturation regime, respectively, corresponding to normally-on and normally-off transfer curve, while the SH-triggering powers are almost identical. The conductor-like channel originates from the SH-induced high donor population, while the disconnection between channel and drain is caused by a highly defective region near drain, where the hot-carrier damage is violently activated by the SH-induced high temperature and the high drain electric field in saturation regime.

Polarizable Nonvolatile Ferroelectric Gating in Monolayer MoS2 Phototransistors.

Given the requirements for power and dimension scaling, modulating channel transport properties using high gate bias is unfavorable due to the introduction of severe leakages and large power dissipation. Hence, this work presents an ultrathin phototransistor with chemical-vapor-deposition-grown monolayer MoS2 as the channel and a 10.2 nm thick Al:HfO2 ferroelectric film as the dielectric. The proposed device is meticulously modulated utilizing an Al:HfO2 nanofilm, which passivates traps and suppresses charge Coulomb scattering with Al doping, efficiently improving carrier transport and inhibiting leakage current. Furthermore, a bipolar pulses excitable polarization method is developed to induce a nonvolatile electrostatic field. The MoS2 channel is fully depleted by the switchable and stable floating gate originating from remanent polarization, leading to a high detectivity of 2.05 × 1011 Jones per nanometer of gating layer (Jones nm-1) and photocurrent on/off ratio >104 nm-1, which are superior to the state-of-the-art phototransistors based on two-dimensional (2D) materials and ferroelectrics. The proposed polarizable nonvolatile ferroelectric gating in a monolayer MoS2 phototransistor promises a potential route toward ultrasensitive photodetectors with low power consumption that boast of high levels of integration.

Electrostatic Gating of Phosphorene Polymorphs.

The ability to directly monitor the states of electrons in modern field-effect transistors (FETs) could transform our understanding of the physics and improve the function of related devices. In particular, phosphorene allotropes present a fertile landscape for the development of high-performance FETs. Using density functional theory-based methods, we have systematically investigated the influence of electrostatic gating on the structures, stabilities, and fundamental electronic properties of pristine and carbon-doped monolayer (bilayer) phosphorene allotropes. The remarkable flexibility of phosphorene allotropes, arising from intra- and interlayer van der Waals interactions, causes a good resilience up to equivalent gate potential of two electrons per unit cell. The resilience depends on the stacking details in such a way that rotated bilayers show considerably higher thermodynamical stability than the unrotated ones, even at a high gate potential. In addition, a semiconductor to metal phase transition is observed in some of the rotated and carbon-doped structures with increased electronic transport relative to graphene in the context of real space Green's function formalism.

Simulation of Indirect Time-of-flight Pixel Using High Frequency Operation Low Voltage Trench Gates

Simulation of Indirect Time-of-flight Pixel Using High Frequency Operation Low Voltage Trench Gates

Threshold voltage uniformity improvement by introducing charge injection tuning for low-temperature poly-Si thin film transistors with metal/oxide/nitride/oxide/silicon structure

Low-temperature poly-Si thin film transistors (TFTs) with a metal/oxide/nitride/oxide/silicon structure were fabricated to investigate the feasibility of suppressing threshold voltage variations between TFTs. By applying relatively high positive and negative gate bias voltages, threshold voltage could be tuned positively and negatively, respectively, by injecting charges into the charge trap layer. Stability of threshold voltage against positive gate bias at a level close to the actual circuit operation was not degraded compared with the case of an as-fabricated TFT. A uniform threshold voltage distribution could be achieved in a preliminary test using 16 TFTs by converging threshold voltages with a target value by tuning the threshold voltage for each TFT.

Oxide Semiconductor Heterojunction Transistor with Negative Differential Transconductance for Multivalued Logic Circuits.

Multivalued logic (MVL) technology is a promising solution for improving data density and reducing power consumption in comparison to complementary metal-oxide-semiconductor (CMOS) technology. Currently, heterojunction transistors (TRs) with negative differential transconductance (NDT) characteristics, which play an important role in the function of MVL circuits, adopt organic or 2D semiconductors as active layers, but it is still difficult to apply conventional CMOS processes. Herein, we demonstrate an oxide semiconductor (OS) heterojunction TR with NDT characteristics composed of p-type copper(I) oxide (Cu2O) and n-type indium gallium zinc oxide (IGZO) using the conventional CMOS manufacturing processes. The electrical characteristics of the fabricated device exhibit a high Ion/Ioff ratio (∼3 × 103), wide NDT ranges (∼29 V), and high peak-to-valley current ratios (PVCR ≈ 25). The electrical properties of 15 devices were measured, confirming uniform performance in the PVCR, NDT range, and Ion/Ioff ratio. We analyze the device operation by varying the source/drain (S/D) position and changing the device geometry and the thickness of the Cu2O layer. Additionally, we demonstrate heterojunction ambipolar TR to elucidate the transport mechanism of NDT devices at a high gate voltage (VGS). To confirm the feasibility of the MVL circuit, we present a ternary inverter with three clearly expressed logic states that have a long intermediate state and greater margin of error induced by wide NDT regions and high PVCR.

High-Frequency Three-Level Gate Driver for GaN HEMT Bridge Crosstalk Suppression

High-Frequency Three-Level Gate Driver for GaN HEMT Bridge Crosstalk Suppression

Frequency-Modulated Charge Pumping: Defect Measurements With High Gate Leakage

Charge pumping is one of the most relied techniques used to quantify interface defects in metal-oxide-semiconductor devices. However, conventional charge pumping is easily hindered by excessive gate leakage currents, which render the technique unsuitable for advanced technology nodes. We demonstrate a new frequency-modulated charge pumping methodology in which we transform the quasi-dc charge pumping measurement into an ac measurement. The ac detection scheme is highly resistant to gate leakage currents and extends the usefulness of charge pumping as a defect monitoring tool for future technologies.

Analysis of Operational Characteristics of AlGaN/GaN MIS-HEMT with Different Slant-Recessed-Gate Structures

Purpose of WorkRecessed-gate metal-insulator-semiconductor high electron mobility transistors (MIS-HEMTs) have emerged as a promising technology for normally-off operation because of their ability to withstand high gate voltage sweeps while maintaining low levels of leakage current [1, 2]. Despite their excellent performance, the etch to leave nanometer-thin layers of AlGaN has proven to be a significant challenge due to difficulties in precisely controlling the etching process. Achieving a positive threshold voltage (Vth) while maintaining the high electron mobility characteristic of the two-dimensional electron gas (2DEG) requires atom-level etch control. Additionally, conventional dry etching techniques can potentially cause damage, presenting a second challenge [3]. However, atomic layer etching (ALE) offers a promising solution with its potential for low damage, uniformity, and high-resolution depth control [4]. In this work, we not only focus on the ALE process to leave nanometer-thin layers of AlGaN/GaN as recessed-gate structures but also analyze the breakdown voltage characteristics of the slant-recessed gate structure.ApproachNormally-off AlGaN/GaN MIS-HEMT with a recessed gate structure was fabricated on a 6-inch commercial Si substrate by MOCVD. The process involved mesa isolation by ICP-RIE, followed by the formation of the ohmic contact (Ti/Al/Ni/Au) at 825 °C annealing for source and drain metals, and the AlGaN/GaN recessed gate structure using ALE technology by O2/BCl3 multiple cycles of oxidation and etching [5]. After the recessed-gate process, the native oxide and carbon residue were removed by a wet cleaning process and O2 plasma treatment, and then the atom layer deposition (ALD) of about 12 nm thickness Al2O3 high-dielectric layer was also deposited. The backend process included gate field plate, SiNx passivation, and contact opening. Finally, the Ni/Au metal stack was deposited as pad electrodes, as shown in Fig. 1. The specific characteristics of the fabricated recessed MIS-HEMT were Lg of 3 μm, Lgs of 5 μm, Lgd of 10 μm, and Wg of 100 μm.Results and SignificanceIn Figure 2(a) and (b), TEM profiles of the recessed gate structure were presented. Following the ALE process for the recessed gate structure, the remaining thickness of AlGaN was approximately 5.1 nm and 5.6 nm for Slant A and Slant B, respectively. Although the thickness of AlGaN remaining was similar in both cases, the slant angle of the recessed gate structure differed, significantly. Specifically, Slant A had a 65-degree recessed gate structure, while Slant B had a 45-degree recessed gate structure. In order to analyze of operational characteristics of AlGaN/GaN MIS-HEMT with different slant-recessed gate structures (Slant A and Slant B), the three-terminal OFF-state breakdown voltage (BV) was measured, as shown in Fig. 3. Recessed gate MIS-HEMT feature design of Lg/Lgd/Lgd/Wg of 3/5/10/100 μm, and VG of -10 V was used as this BV measured condition. The Slant B structure demonstrated higher breakdown voltage (BV) performance compared to the Slant A structure. Specifically, the Slant B structure exhibited a BV of 470 V at 1 μA/mm and 750 V at 1 mA/mm, while the Slant A structure had a BV of only 70 V at 1 μA/mm and 140 V at 1 mA/mm. The reason for the superior BV performance of the Slant B structure (45-degree recessed gate structure) was attributed to the gradient of the AlGaN profile, which facilitates the thin film deposition process of materials such as Al2O3 and gate metal (Ni/Au). Additionally, the Slant B structure helps to reduce the high electric field effect between the gate and drain, further contributing to its improved BV performance.[1] Y. S. Lin, Y. W. Lain, and S. S. H. Hsu, "AlGaN/GaN HEMTs With Low Leakage Current and High On/Off Current Ratio," IEEE Electron Device Letters, vol. 31, no. 2, pp. 102-104, 2010.[2] Z. Tang et al., "600-V Normally Off SiNx/AlGaN/GaN MIS-HEMT With Large Gate Swing and Low Current Collapse," IEEE Electron Device Letters, vol. 34, no. 11, pp. 1373-1375, 2013.[3] T. H. Hung, P. S. Park, S. Krishnamoorthy, D. N. Nath, and S. Rajan, "Interface Charge Engineering for Enhancement-Mode GaN MISHEMTs," IEEE Electron Device Letters, vol. 35, no. 3, pp. 312-314, 2014.[4] T. Y. Yang et al., "A Normally-Off GaN MIS-HEMT Fabricated Using Atomic Layer Etching to Improve Device Performance Uniformity for High Power Applications," IEEE Electron Device Letters, vol. 43, no. 10, pp. 1629-1632, 2022.[5] I.-H. Hwang, H.-Y. Cha, and K.-S. Seo, "Low-Damage and Self-Limiting (Al)GaN Etching Process through Atomic Layer Etching Using O2 and BCl3 Plasma," Coatings, vol. 11, no. 3, p. 268, 2021. Figure 1

Gate leakage suppression of normally-OFF diamond FET by employing MOS-MES hybrid gate structure

Normally-off filed-effect transistors (FETs) are critical for logical circuit and switch systems. However, the presence of two-dimensional holes in hydrogen-terminated diamond (CH diamond) makes most of regular CH diamond MOSFETs normally-ON operation, leading to energy loss. Metal-semiconductor (MES) FETs with Schottky gate are a good way to achieve normally-off CH diamond FETs, but have the disadvantage of high gate leakage current. In this work, a MOS-MES hybrid gate diamond FET with normally-off operation and low gate leakage current was fabricated by adding nanoparticles Al2O3 (nano-Al2O3) between Al/C-H diamond interface. The MES formed by Al/C-H diamond plays the role of realizing normally-off operation, and the MOS of Al/nano-Al2O3/C-H diamond is used to lower the gate leakage current. 100 % of hybrid gate devices displayed normally-off operation with threshold voltages ranging from −0.2 V to −1.2 V, as well as the gate leakage current is 103-106-fold lower than that of FET without nano-Al2O3. The hybrid gate structure is poised to become a part of the FET community.