High Gate Bias Stress Research Articles

Comprehensive Investigation of Gate Oxide Instability in 4H-SiC MOSFETs and MOS Capacitors Under High Gate Bias Stress

Comprehensive Investigation of Gate Oxide Instability in 4H-SiC MOSFETs and MOS Capacitors Under High Gate Bias Stress

Improving the High-Temperature Gate Bias Instabilities by a Low Thermal Budget Gate-First Process in p-GaN Gate HEMTs

In this study, we report a low ohmic contact resistance process on a 650 V E-mode p-GaN gate HEMT structure. An amorphous silicon (a-Si) assisted layer was inserted in between the ohmic contact and GaN. The fabricated device exhibits a lower contact resistance of about 0.6 Ω-mm after annealing at 550 °C. In addition, the threshold voltage shifting of the device was reduced from -0.85 V to -0.74 V after applying a high gate bias stress at 150 °C for 10-2 s. The measured time to failure (TTF) of the device shows that a low thermal budget process can improve the device's reliability. A 100-fold improvement in HTGB TTF was clearly demonstrated. The study shows a viable method for CMOS-compatible GaN power device fabrication.

Characterization and analysis of low-temperature time-to-failure behavior in forward-biased Schottky-type p-GaN gate HEMTs

The low-temperature gate reliability of Schottky-type p-GaN gate AlGaN/GaN heterojunction field-effect transistors under forward gate voltage stress is investigated. Both temperature-accelerated and voltage-accelerated time-dependent gate breakdown stress experiments are performed. The p-GaN gate exhibits a shorter time-to-failure at a lower temperature. It is found that the time-to-failure at “use conditions” predicted by acceleration tests at high gate bias stress could be overestimated at low temperatures. Such a discrepancy stems from the distinct dominant gate leakage mechanisms at high/low gate bias stress conditions. The dominant physical mechanism of the low-temperature gate leakage current is identified to be Poole–Frenkel emission at low gate bias and Fowler–Nordheim tunneling at high bias. From the physical model, a more accurate lifetime projection can be obtained for given use conditions.

Lifetime prediction of InGaZnO thin film transistor for the application of display device and BEOL-transistors

In this work, the lifetime prediction models of amorphous InGaZnO thin film transistors (a-IGZO TFTs) were suggested for the application of display device and BEOL (Back End Of line) transistors with embedded a-IGZO TFTs. Four different types of test devices according to the active layer thickness, source/drain electrode materials and thermal treatments have been used to verify the suggested model. The device lifetimes under high gate bias stress and hot carrier stress were extracted through fittings of the stretched-exponential equation for threshold voltage shifts and the current estimation method for drain current degradations. Our suggested lifetime prediction models could be used in any kinds of structures of a-IGZO TFTs for the application of display device and BEOL transistors. The a-IGZO TFTs with embedded ITO local conducting layer under source/drain is better for BEOL transistor application and a-IGZO TFTs with InGaZnO thin film as source/drain electrodes may be better for the application of display devices.

P‐21: n‐type Organic Thin Film Transistors with High Operational Stability

Abstractn‐type organic thin film transistors (OTFTs) with high operational stability was demonstrated. The operational stability of N,N′‐ditridecylperylene‐3,4,9,10‐tetracarboxylic diimide (PTCDI‐C13)‐based OTFTs was improved by engineering organic semiconductor‐gate insulator interface with hydrophobic polymers. Under high gate bias stress (equivalent to the electric field of 3MV/cm) for two hours, OTFTs with hydrophobic polymers showed small threshold voltage shift around 2 V. Moreover, the electron mobility was improved from 0.038 to 0.14–0.15 cm2/Vs with hydrophobic polymers.

Overcoming tradeoff between mobility and bias stability in organic field-effect transistors according to the self-assembled monolayer chain lengths

This study examined the relationship between the mobility and bias stability of pentacene-based organic field-effect transistors (OFETs) regarding a self-assembled monolayer (SAM) treatment. For this systematic study, four types of silazane-based SAMs with different alkyl chain lengths in the range of 1–8 were used. Silazane-based SAMs have an advantage of processability due to the mild reaction conditions. The mobility was increased from 0.29 without SAM to 0.46, 0.61, 0.65, and 0.84 cm2/V s after the SAM-treatment with an alkyl chain length of 1, 3, 4, and 8, respectively. On the other hand, inverse proportional relationship was observed between the bias stability and SAM alkyl chain length. Under high gate bias stress (equivalent to electric field of 3 MV/cm) for 2 h, the threshold voltage shift of the OFET was decreased from 12.19 V without SAM to 5.69 V with a short SAM-treatment (alkyl chain length of 1) and 7.14 V with a long SAM-treatment (alkyl chain length of 8). This is the significant finding that there was a tradeoff relationship between the mobility and bias stability of OFETs concerning the SAM alkyl chain length. To overcome this tradeoff, a method for surface engineering using two-step SAM-treatment was introduced. By treating long SAM and short SAM in sequence, both the high mobility and good bias stability were achieved. With two-step SAM-treatment, the OFET showed high mobility as a long SAM-treated OFET and good bias stability as a short SAM-treated OFET.

P.64: WITHDRAWN: P.65: The Effect of Surface Polarity of Gate Dielectric Buffer Layer on Operational Stability in Organic Thin Film Transistors

AbstractWe studied the effect of surface polarity of gate dielectric buffer layer on operational stability in organic thin film transistors (OTFTs). By employing four types of polymers with different polarity, we found out the operational stability of OTFTs can be improved with low‐polarity polymer gate dielectric buffer layer. With low‐polarity polymers, the devices showed good operational stability with longer relaxation time than 106 sec. Also, threshold voltage of the devices shifted less than 2 V under high gate bias stress of 3 MV/cm for two hours. Good stability may be resulted from low surface trap density as well as good grain interconnection of pentacene on low‐polarity polymer.

Instability of threshold voltage under constant bias stress in pentacene thin film transistors employing polyvinylphenol gate dielectric

The instability of threshold voltage and mobility of pentacene thin film transistors using a poly(4-vinylphenol) gate dielectric have been investigated under constant bias stress. The mobility was very stable in vacuum by exhibiting 2% variation after 6 h stress even under the high gate bias stress of V GS = − 20 V. Meanwhile, we observe a negative shift of threshold voltage under stress in vacuum. This shift is attributed to charges trapped in deep electronic states in pentacene near the gate interface. We propose a model for the negative shift of the threshold voltage and extract the hole concentration, 4.5 × 10 11 cm − 2 , needed to avoid the onset of stress effects, resulting in a design rule of the channel width to length ratio larger than 40.

Effect of synchrotron X-ray radiation on the channel hot-carrier reliability of reoxidized nitrided silicon dioxide

Channel hot-carrier-induced degradation was studied in reoxidized nitrided oxide n-channel MOSFETs which were exposed to 1-2-keV X-rays from a synchrotron source. It is found that transconductance degradation under high gate bias stress (Vg=1.3 V/sub d/) is enhanced by the X-ray exposure to a lesser degree in reoxidized nitrided oxide (RNO) devices than in conventional oxide devices. This indicates that radiation generates fewer electron traps in RNO than in a conventional oxide. >