High-gain Operational Transconductance Amplifier Research Articles

A very low-power discrete-time delta-sigma modulator for wireless body area network

This paper proposes a very low-power discrete-time delta-sigma modulator (DTDSM) for the wireless body area network (WBAN) which deals with biomedical signals. The first stage integrator is optimized using correlated double sampling technique and is implemented using a high-gain designed telescopic operational transconductance amplifier (OTA) in order to maintain the proposed second-order DTDSM high resolution. In order to keep both stage integrators active and prevent ENOB loss, a very low power two-stage charge-steering amplifier is employed in the second stage integrator which leads to a power efficient design. Due to not high but enough voltage-gain of this type of amplifier, the proposed charge-steering-based integrator leads to a negligible loss of ENOB in comparison to passive integrators with no voltage gain which are commonly used in the second stage to reduce the total power. In fact, due to the combination of a high-gain OTA in first stage integrator and a low-power charge-steering amplifier in second stage, compromise between high resolution and low power consumption will be depicted.The proposed DTDSM is designed for a signal bandwidth of 50 kHz with an oversampling ratio of 128 for implantable biomedical devices in the MICS band. Simulations are done using TSMC 180 nm technology at a 1.8 V power supply. Simulation results illustrate that the designed modulator achieves an SNR of 56 dB which is equal to 9 bits of ENOB that is in the desired range for biomedical signals. The power consumption of this modulator is only 142 μW at a 12.5 MHz sampling frequency.

Design of Low Voltage Low Power High Gain Operational Transconductance Amplifier

In this paper, a high gain structure of operational transconductance amplifier is presented. For low voltage operation with improved frequency response bulk driven quasi-floating gate MOSFET is used at the input. Further for achieving high gain the modified self cascode structure is used at the output. Compared to conventional self cascode the modified self cascode structure used provides higher transconductance which helps in significant boosting of gain of the amplifier. The modification is achieved by employing quasi-floating gate transistor which helps in scaling of the threshold which as a result increases the drain-to-source voltage of linear mode transistor thus changing it to saturation. This change of mode boosts the effective transconductance of self cascode MOSFET. The proposed operational transconductance amplifier when compared to its conventional showed improvement in DC gain by 30dB and also the unity gain bandwidth increases by 6 fold. The MOS models used for amplifier design are of 0.18µm CMOS technology at supply of 0.5V.

A Low-Noise High-Gain Recycling Folded Cascode Operational Transconductance Amplifier Based on Gate Driven and Quasi-Floating Bulk Technique

Operational Transconductance Amplifier (OTA) is an important circuit block used in the design of filter, amplifiers and oscillators for various analog-mixed circuit systems. However, design of a low-noise, high-gain OTA with low-power consumption is a challenging task in CMOS technology owing to high-power requirements of OTA for emulating high gain. This paper represents the design of gate-driven quasi-floating bulk recycling folded cascode (GDQFB RFC) OTA which has been shown to provide low-noise operation, emulates high gain and draws very less power. The design utilizes the gate-driven quasi-floating bulk (GDQFB) technique on a recycling folded cascode structure, which enhances the transconductance of OTA and improves its performance. All the post-layout simulation results have been obtained in 0.18-μm CMOS N-well technology using BSIM3V3 device models. The obtained results indicate very high gain of 100.4 dB, gain-bandwidth of 69 kHz, phase margin of 51.9∘ with power consumption of 2.31μW from ±0.9V supply voltage. The input referred noise emulated by proposed OTA is 0.684, 0.21 and 0.0592μV/√Hz @ 1 Hz, 10 Hz and 1 kHz, respectively. The input common mode range and output voltage swing are found to be −0.402 to 0.669 V and −0.493 to 0.610 V, respectively. Corner simulations and Monte Carlo analysis have been performed to verify the robustness of the proposed OTA. The proposed OTA can be used in design of filters and amplifiers for bio-instruments, sensor applications, neural recording applications and human implants etc.

A low-power, high-resolution, adaptive sensitivity readout circuit with selective detection range for capacitive biosensors

In this paper, the design and implementation of a low-power, high-resolution, fully differential readout architecture for capacitive sensing applications is presented. The proposed sensing mechanism is based on the gain variations of two capacitively coupled operational transconductance amplifiers (OTAs). The target analyte acts as the dielectric of a sensing electrode, and its detection results in capacitance variations. These capacitance variations are translated to voltage, and the result is amplified to be used as a biomarker detector. With high-gain OTAs and a high-gain difference amplifier, the proposed mechanism achieves a high-resolution of 1aF, with a sensitivity of 290mV/fF. The proposed structure exhibits such a high-resolution while maintains an extremely low-power consumption of 6.6μW. Using perfectly matched elements with accurate layout, this structure is able to reduce the mismatch-based errors to less than 0.05%. An 8-bit control word adjusts the sensitivity and the detection range of the proposed structure which results in a wide dynamic range of 100dB. The main features of the proposed structure such as high-resolution, high-sensitivity, low-power consumption, selective capacitance detection range and adaptive sensitivity, make this readout mechanism an ideal solution for sensitive, low-power, and accurate life science biosensors.

Synthesis of High Gain Operational Transconductance Amplifiers for Closed-Loop Operation Using a Generalized Controller-Based Compensation Method

This paper presents a systematic procedure that can be used to create operational transconductance amplifiers (OTAs) for closed-loop operation using multiple low-gain stages to realize extremely high DC gain. Such devices are necessary to realize analog functions with demanding absolute accuracy requirements, e.g., high-resolution ADCs and DACs. The principle is based on the cascade of undamped integrators to realize large DC gains and a state-space derived controller to stabilize its operation in a closed-loop configuration. A programmable OTA fabricated in the IBM 130 nm CMOS process is used as a test vehicle to prove the design principle through its 2 to 5th-order realization. Measured data reveals DC gains ranging from 50 to 150 dB with a 3-dB bandwidth of 10 kHz and a unity gain frequency of 10 MHz. While this paper demonstrates the design principles using CMOS integrated circuits, the principle is general and can be applied to any type of circuit technology in integrated or discrete implementation. Moreover, the methods are easily automated as the principles are based on closed-form formulae as opposed to iterative numerical search techniques.

Low Power and High Gain Operational Transconductance Amplifier

A Positive feedback method for operational transconductance amplifiers is proposed operating at subthreshold region. In this paper a differential amplifier has designed with gain enhancement technique using positive feedback. The proposed circuit has improved specifications such as high DC gain, low power dissipation as compared to previous work. We designed CMOS OTA in a UMC 180nm technology powered with 1.8V exhibits 91.23-dB DC gain while consuming 35.72nW.

A simple structure for noise-shaping SAR ADC in 90 nm CMOS technology

This paper presents a simple structure for error feedback based noise-shaping successive approximation register (NSSAR) analog-to-digital converter (ADC), which obviates the need for a high output swing, fast-settling and high gain Operational Transconductance Amplifier (OTA). The ADC has a simple structure and its quantization noise is extracted and transferred via a finite impulse response (FIR) filter, without any attenuation. To make a good matching, a 5-bit segmented array is utilized as a digital-to-analog converter (DAC). In this way, the required total capacitance of the ADC is reduced more than 96% compared to a 10-bit conventional SAR (CSAR) ADC. Also, due to noise-shaping property the comparator specifications are relaxed. The ADC is designed and simulated in 90nm CMOS technology with HSPICE simulator. Simulation results show that the ADC's average power consumption is about 4.4μW at a 0.5V power supply. By using an oversampling ratio (OSR) of 16, the ADC achieved maximum SNDR and SFDR of 59.6dB and 58dB, respectively, from transient noise simulation. The figure of merit (FoM) is about 56.4fJ/conversion-step.

High-Gain Operational Transconductance Amplifiers in a Printed Complementary Organic TFT Technology on Flexible Foil

This paper presents the design and experimental results of advanced analog blocks manufactured in a printed complementary organic TFT technology on flexible foil. Operational transconductance amplifiers exhibiting open-loop gain from 40 to 50 dB and gain-bandwidth product from 55 Hz to 1.5 kHz have been implemented by using different circuit topologies. An extensive amplifier characterization in both time and frequency domain (i.e., gain, gain-bandwidth product, phase margin, settling time, harmonic distortion) has been carried out, which demonstrates the performance of the adopted technology in analog circuit implementations. Finally, a 40-dB 1.5-kHz amplifier has been employed in a switched capacitor comparator that proved fully functionality up to input frequency of 50 Hz.

A 24.5 mW, 10-bit, 50 MS/sec CMOS pipelined analogue-to-digital converter

This paper presents the design of a low-power, medium-resolution, high-speed pipelined analogue-to-digital converter (ADC). A low-power front-end track-and-hold amplifier (THA) is realised to reduce sampling time uncertainty error. The paper also includes the design of low-power, high-bandwidth, high-gain operational transconductance amplifiers (OTAs). The OTAs are used in ADC to reduce finite OTA gain and OTA settling time non-linearity errors. Low power circuit techniques are employed to minimise overall power consumption of the ADC. The proposed ADC is implemented in 180 nm digital CMOS technology. The converter achieves signal-to-noise distortion ratio of 59.8 dB/57.9 dB, spurious-free dynamic range of 89 dB/86.6 dB and effective number of bits of 9.64-bits/9.33-bits at sampling speed of 50 MHz with the input signal frequencies of 4 MHz/Nyquist frequency. The peak differential-non-linearity of the converter is 0.28/-0.17 LSB and integral-non-linearity of the converter is +0.42/-0.41 LSB. The proposed 10-bit, 50 MS/sec pipelined ADC consumes 24.5 mW amount of power from 1.8 V supply.