High Frequency Divider Research Articles

High-speed CMOS Frequency Divider with Inductive Peaking Technique

This work proposes an integrated high frequency divider with an inductive peaking technique implemented in a current mode logic (CML) frequency divider. The proposed divider is composed with a master-slave flip-flop, and the master-slave flip-flop acts as a latch and read circuits which have the differential pair and cross-coupled n-MOSFETs. The cascode bias is applied in an inductive peaking circuit as a current source and the cascode bias is used for its high current driving capability and stable frequency response. The proposed divider is designed with 0.18-μm CMOS process, and the simulation used to evaluate the divider is performed with phase-locked loop (PLL) circuit as a feedback circuit. A divide-by-two operation is properly performed at a high frequency of 20 GHz. In the output frequency spectrum of the PLL, a peak frequency of 2 GHz is obtained witha divide-by-eight circuit at an input frequency of 250 MHz. The reference spur is obtained at -64 dBc and the power consumption is 13 mW.

A Novel, Low-Voltage, Current Reused, Quadrature VCO and Divide-by-4 Frequency Divider Circuit

A low-voltage, current-reused, quadrature voltage controlled oscillator (QVCO) and divide-by-4 frequency divider (FD4) architecture is presented for the first time. The proposed architecture features compact and low voltage operation by the proper stacking of a ring-type injection locked FD4 and a back-gate coupled QVCO. This design lowers the power consumption and eliminates the need of high frequency divider as well as buffering stage. The circuit has been implemented in 0.18-μm triple-well CMOS process. Experimental results show a phase noise level of -114.1 dBc/Hz at 1 MHz offset from carrier (2.2 GHz). This chip occupies a core area of 0.9×0.35 mm2 and consumes 2.7 mA from a 1.3 V power supply.

A 3.1–4.8 GHz transmitter with a high frequency divider in 0.18 μm CMOS for OFDM-UWB

A fully integrated low power RF transmitter for a WiMedia 3.1–4.8 GHz multiband orthogonal frequency division multiplexing ultra-wideband system is presented. With a separate transconductance stage, the quadrature up-conversion modulator achieves high linearity with low supply voltage. The co-design of different resonant frequencies of the modulator and the differential to single (D2S) converter ensures in-band gain flatness. By means of a series inductor peaking technique, the D2S converter obtains 9 dB more gain without extra power consumption. A divided-by-2 divider is used for carrier signal generation. The measurement results show an output power between −10.7 and −3.1 dBm with 7.6 dB control range, an OIP3 up to 12 dBm, a sideband rejection of 35 dBc and a carrier rejection of 30 dBc. The ESD protected chip is fabricated in the Jazz 0.18 μm RF CMOS process with an area of 1.74 mm2 and only consumes 32 mA current (at 1.8 V) including the test associated parts.

High frequency dividing synchronous oscillator using modified emitter couple logic inverters

A synchronous oscillator using a high speed low-voltage emitter coupled logic (ECL) inverter has been reported. Using the positive feedback the locking range increases, compared to the oscillator without any positive feedback. A maximum improvement (increase) of percentage locking range of around 105% was obtained from circuit simulation as well as from practical circuit, using discrete components. Because the locking range is maximum at double the output frequency of the oscillator, this oscillator can be used as a high frequency divider circuit. The circuit requires a supply voltage of 2.1 V.