High Frequency Capacitance-voltage Measurements Research Articles

Charging Effects in Al-SiO2-p-Si Structures After Low-Energy Electron Beam Irradiation

The effect of electron beam irradiation on trap charging and interface defect generation in Al/SiO2/Si structures was investigated by high-frequency capacitance–voltage measurements. Irradiation was carried out with two beam energies, at which the electron penetration depth was smaller and larger than the SiO2 thickness. The effect of applied bias, which changes the electric field inside the SiO2 film and the Si surface potential, on both the interface defect generation under the electron beam irradiation and their annealing was revealed. This showed that excess electrons generated by an e-beam play an important role in the interface defect formation. It was found that interface trap relaxation can occur even at room temperature, likely by electron tunneling from Si or hole tunneling from SiO2. The relaxation of positive bulk charge occurs at temperatures higher than 400 K via thermally stimulated carrier escape from traps. The activation energy for this process was estimated as 0.35–0.4 eV.

Determination of the Parameters of Metal–Insulator–Semiconductor Structures with Ultrathin Insulating Layer from High-Frequency Capacitance–Voltage Measurements

A simple numerical method for processing the data of the high-frequency capacitance–voltage characteristics of metal–insulator–semiconductor structures is proposed. The approach is based on analyzing the experimental characteristics near the flat-band states, where the charge exchange of surface localized electron states is of little importance compared with changes in the near-boundary charged layer in the semiconductor. The developed technique makes it possible, first, to find the necessary parameters of the semiconductor and insulating layer and, second, to obtain the experimental field dependences of the energy-band bending in the semiconductor and the total concentration of the built-in charge, the charge of boundary states and minority charge carriers at the semiconductor–insulator interface in the range from the flat bands to deep depletion. The technique is well applicable to structures with an ultra-thin insulating layer. On n-Si-based metal–oxide–semiconductor samples with an oxide thickness of 39 A, experimental approbation of the proposed approach is carried out. The accuracy of the obtained results is 2–3%.

Capacitance–Frequency Estimates of Border-Trap Densities in Multifin MOS Capacitors

We use capacitance–frequency ( $C$ – $f$ ) measurements to provide lower bound estimates of border-trap densities in multifin MOS capacitors with high-K dielectrics built in Ge and InGaAs fin field effect transistor (FinFET) technologies before and after X-ray irradiation. The $C$ – $f$ method is illustrated for SiO2-based planar MOS capacitors and compared with high-frequency capacitance–voltage measurements. Lower effective border-trap densities are found before and after irradiation for multifin capacitors built in a strained Ge $p$ MOS FinFET technology than for similar devices built using an early-developmental stage InGaAs MOS technology. These results show the utility of $C$ – $f$ measurements in characterizing defect densities in MOS capacitors, particularly when large border-trap densities exist.

Interface Electrical Properties of Al2O3 Thin Films on Graphene Obtained by Atomic Layer Deposition with an in Situ Seedlike Layer.

High-quality thin insulating films on graphene (Gr) are essential for field-effect transistors (FETs) and other electronics applications of this material. Atomic layer deposition (ALD) is the method of choice to deposit high-κ dielectrics with excellent thickness uniformity and conformal coverage. However, to start the growth on the sp2 Gr surface, a chemical prefunctionalization or the physical deposition of a seed layer are required, which can effect, to some extent, the electrical properties of Gr. In this paper, we report a detailed morphological, structural, and electrical investigation of Al2O3 thin films grown by a two-steps ALD process on a large area Gr membrane residing on an Al2O3-Si substrate. This process consists of the H2O-activated deposition of a Al2O3 seed layer a few nanometers in thickness, performed in situ at 100 °C, followed by ALD thermal growth of Al2O3 at 250 °C. The optimization of the low-temperature seed layer allowed us to obtain a uniform, conformal, and pinhole-free Al2O3 film on Gr by the second ALD step. Nanoscale-resolution mapping of the current through the dielectric by conductive atomic force microscopy (CAFM) demonstrated an excellent laterally uniformity of the film. Raman spectroscopy measurements indicated that the ALD process does not introduce defects in Gr, whereas it produces a partial compensation of Gr unintentional p-type doping, as confirmed by the increase of Gr sheet resistance (from ∼300 Ω/sq in pristine Gr to ∼1100 Ω/sq after Al2O3 deposition). Analysis of the transfer characteristics of Gr field-effect transistors (GFETs) allowed us to evaluate the relative dielectric permittivity (ε = 7.45) and the breakdown electric field (EBD = 7.4 MV/cm) of the Al2O3 film as well as the transconductance and the holes field-effect mobility (∼1200 cm2 V-1 s-1). A special focus has been given to the electrical characterization of the Al2O3-Gr interface by the analysis of high frequency capacitance-voltage measurements, which allowed us to elucidate the charge trapping and detrapping phenomena due to near-interface and interface oxide traps.

Characterization of Graphene Gate Electrodes for Metal-Oxide-Semiconductor Devices

ABSTRACT We fabricate and characterize metal-oxide-semiconductor (MOS) devices with graphene as the gate electrode, 5 or 10 nm thick silicon dioxide as the insulator, and silicon as the semiconductor substrate. We find that Fowler-Nordheim tunneling dominates the gate current for the 10 nm oxide device. We also study the temperature dependence of the tunneling current in these devices in the range 77 to 300 K and extract the effective tunneling barrier height as a function of temperature for the 10 nm oxide device. Furthermore, by performing high frequency capacitance-voltage measurements, we observe a local capacitance minimum under accumulation, particularly for the 5 nm oxide device. By fitting the data using numerical simulations based on the modified density of states of graphene in the presence of charged impurities, we show that this local minimum results from the quantum capacitance of graphene. These results provide important insights for the heterogeneous integration of graphene into conventional silicon technology.

Gate tunneling current and quantum capacitance in metal-oxide-semiconductor devices with graphene gate electrodes

Metal-oxide-semiconductor (MOS) devices with graphene as the metal gate electrode, silicon dioxide with thicknesses ranging from 5 to 20 nm as the dielectric, and p-type silicon as the semiconductor are fabricated and characterized. It is found that Fowler-Nordheim (F-N) tunneling dominates the gate tunneling current in these devices for oxide thicknesses of 10 nm and larger, whereas for devices with 5 nm oxide, direct tunneling starts to play a role in determining the total gate current. Furthermore, the temperature dependences of the F-N tunneling current for the 10 nm devices are characterized in the temperature range 77–300 K. The F-N coefficients and the effective tunneling barrier height are extracted as a function of temperature. It is found that the effective barrier height decreases with increasing temperature, which is in agreement with the results previously reported for conventional MOS devices with polysilicon or metal gate electrodes. In addition, high frequency capacitance-voltage measurements of these MOS devices are performed, which depict a local capacitance minimum under accumulation for thin oxides. By analyzing the data using numerical calculations based on the modified density of states of graphene in the presence of charged impurities, it is shown that this local minimum is due to the contribution of the quantum capacitance of graphene. Finally, the workfunction of the graphene gate electrode is extracted by determining the flat-band voltage as a function of oxide thickness. These results show that graphene is a promising candidate as the gate electrode in metal-oxide-semiconductor devices.

The influence of La/Al atomic ratio on the dielectric constant and band-gap of stack-gate La–Al–O/SiO2 structure

The influence of La/Al atomic ratio on high-dielectric-constant of La–Al–O thin films deposited by atomic layer deposition is investigated. The uniform surface morphology of the bilayer films with different La/Al cycle ratio (La/Al ratio) is observed after rapid thermal annealing. With the help of high-frequency capacitance–voltage measurement, the dielectric constant drops greatly with decreasing La/Al ratio. It is caused by the formation of La(OH)3 in La–Al–O thin film, which has been verified by X-ray photoelectron spectroscopy (XPS) measurement. For the reduced interface dipoles at the high-k/SiO2 interface, the flat band voltage (Vfb) shift is not obvious in La–Al–O film. By ellipsometry measurements, it can be found that the band-gap of the thin film increases with increasing Al component, especially when Al component in La–Al–O gate dielectric is small. The research results here show that lower Al doping in La–Al–O can keep high dielectric constant and relatively large band-gap in the thin film, which is very useful for the high-k process development.

Impact of interstitial oxygen trapped in silicon during plasma growth of silicon oxy-nitride films for silicon solar cell passivation

Low temperature oxidation of silicon in plasma ambient is a potential candidate for replacing thermally grown SiO2 films for surface passivation of crystalline silicon solar cells. In this work, we report the growth of silicon oxy-nitride (SiOxNy) film in N2O plasma ambient at 380 °C. However, this process results in trapping of interstitial oxygen within silicon. The impact of this trapped interstitial oxygen on the surface passivation quality is investigated. The interstitial oxygen trapped in silicon was seen to decrease for larger SiOxNy film thickness. Effective minority carrier lifetime (τeff) measurements on n-type float zone silicon wafers passivated by SiOxNy/silicon nitride (SiNv:H) stack showed a decrease in τeff from 347 μs to 68 μs, for larger SiOxNy film thickness due to degradation in interface properties. From high frequency capacitance-voltage measurements, it was concluded that the surface passivation quality was governed by the interface parameters (fixed charge density and interface state density). High temperature firing of the SiOxNy/SiNv:H stack resulted in a severe degradation in τeff due to migration of oxygen across the interface into silicon. However, on using the SiOxNy/SiNv:H stack for emitter surface passivation in screen printed p-type Si solar cells, an improvement in short wavelength response was observed in comparison to the passivation by SiNv:H alone, indicating an improvement in emitter surface passivation quality.

Study of the Chemical and Morphological Characteristics of Al2O3 and HfO2 Surfaces after Immersion in Time-Dependent pH Solutions

The chemical and morphological characteristics of ALD Al2O3 and HfO2 layers after the immersion in no-buffer pH solutions have been obtained. These films are usually used as sensing layers in chemical sensors applications, and the morphology and chemical characteristics are of great importance to the chemicall sensitivity which they can provide. Hence, morphological changes has been recorded by atomic force microscopy (AFM), while the chemical characteristics has been obtained by Fourirer Transform Infrared Spectroscopy (FTIR). Also, the electrical characteristics, which need to be of high quality in ion-sensing applications, has been determined by High-Frequency Capacitance Voltage (C-V) measurements in Metal-Insulator-Metal capacitors (MIM). The results suggest that the changes experienced by the films under immersion are highly time and ionstrenght dependent, and this might be the main cause of drift in ionsensitive solid state sensors. Moreover, the data shows that HfO2 and Al2O3 exihibit different chemical characteristics after immersion than Si3N4, nonetheless, due to their high chemical sensitivity and higher dielecric constant these materials are well suited for applications in ion-sensing devices.

A model for the frequency dispersion of the high-k metal-oxide-semiconductor capacitance in accumulation

High-frequency capacitance-voltage measurements have been made on metal-oxide-semiconductor capacitors by using single crystalline Er2O3 high-k gate dielectrics. Based on our analysis, it has been found that frequency dispersion of Er2O3 capacitance in accumulation decreases consistently with the increase of the frequency. A correction model is proposed to explain these frequency dispersion phenomena and the capacitance-frequency equations are obtained from the impedance expression of the equivalent circuit. Based on the simulated capacitance-frequency, it can be concluded that frequency dispersion of Er2O3 capacitance in accumulation originates from the existence of the parasitic resistances, the series resistances, and the formed SiOx interfacial layer.

Structural and electrical studies of ultrathin layers with Si0.7Ge0.3 nanocrystals confined in a SiGe/SiO2 superlattice

In this work, SiGe/SiO2 multi-layer (ML) films with layer thickness in the range of a few nanometers were successfully fabricated by conventional RF-magnetron sputtering at 350 °C. The influence of the annealing treatment on SiGe nanocrystals (NCs) formation and crystalline properties were investigated by Raman spectroscopy and grazing incidence x-ray diffraction. At the annealing temperature of 800 °C, where well defined SiGe NCs were observed, a thorough structural investigation of the whole ML structure has been undertaken by Rutherford backscattering spectroscopy, grazing incidence small angle x-ray scattering, high resolution transmission electron microscopy, and annular dark field scanning transmission electron microscopy. Our results show that the onset of local modifications to the ML composition takes place at this temperature for annealing times of the order of a few tens of minutes with the formation of defective regions in the upper portion of the ML structure. Only the very first layers over the Si substrate appear immune to this problem. This finding has been exploited for the fabrication of a defect free metal-oxide-semiconductor structure with a well-defined single layer of SiGe NCs. A memory effect attributed to the presence of the SiGe NCs has been demonstrated by high frequency capacitance-voltage measurements.

Electrical properties of nickel electrodes for high-k MOS structures

Together with high-κ dielectric films, metal gate electrodes have to be employed in advanced CMOS technologies. The metal gate material should be carefully selected with respect to work function, stability of metal-dielectric stack and compatibility with the CMOS process. In our investigation Ni gate electrodes grown on thermal SiO2, atomic-layer deposition HfO2 and Al2O3 dielectric films have been analyzed by means of high-frequency capacitance–voltage measurement on MOS capacitors. Ni gate materials were prepared by RF diode sputter deposition. Work function of the investigated gate material and density of effective defect charge of the gate oxide film were extracted from the measurements. These properties are discussed with regard to application of Ni metal gates in CMOS technology.

Fabrication of nano-floating gate memories through atomic layer deposition incorporated with chemically-synthesized ZnO-nanocrystals

Nano-floating gate memories made of Al 2O 3/ZnO/Al 2O 3 nanostructures were fabricated with chemically-driven ZnO nanocrystals embedded into high-k Al 2O 3 thin films prepared through atomic layer deposition. The memory characteristics were analyzed through high-frequency capacitance–voltage measurement and current–voltage characteristics, along with high-resolution images of the aforementioned structures. The dotted ZnO nanocrystals function as charge-trapping/detrapping centers, inducing a very large memory window of 5.34 V. The defective nature of ZnO was optimally adjusted into the energy-band diagrams in combination with the tunneling and control layers of the robust Al 2O 3 thin films. The measured memory characteristics exhibited superior retention features derived from the charge-trapping/detrapping behaviors.

Effects of post-deposition annealing temperature and ambient on RF magnetron sputtered Sm2O3 gate on n-type silicon substrate

Samarium oxide (Sm2O3) thin films with thicknesses in the range of 15–30 nm are deposited on n-type silicon (100) substrate via radio frequency magnetron sputtering. Effects of post-deposition annealing ambient [argon and forming gas (FG) (90% N2 + 10% H2)] and temperatures (500, 600, 700, and 800 °C) on the structural and electrical properties of deposited films are investigated and reported. X-ray diffraction revealed that all of the annealed samples possessed polycrystalline structure with C-type cubic phase. Atomic force microscope results indicated root-mean-square surface roughness of the oxide film being annealed in argon ambient are lower than that of FG annealed samples, but they are comparable at the annealing temperature of 700 °C (Argon—0.378 nm, FG—0.395 nm). High frequency capacitance–voltage measurements are carried out to determine effective oxide charge, dielectric constant and semiconductor-oxide interface trap density of the annealed oxide films. Sm2O3 thin films annealed in FG have smaller amount of effective oxide charge and semiconductor-oxide interface trap density than those oxide films annealed in argon. Current–voltage measurements are conducted to obtain barrier heights of the annealed oxide films during Fowler–Nordheim tunneling.

Multiferroic Bi 0.7Dy 0.3FeO 3 thin films directly integrated on Si for integrated circuit compatible devices

Magnetoelectric multiferroic Bi 0.7Dy 0.3FeO 3 (BDFO) thin films deposited on p-type Si (100) substrate using pulsed laser deposition technique demonstrated a saturated ferroelectric and ferromagnetic hysteresis loop at room temperature. More interestingly, the observed change in electric polarization with applied magnetic field in these films indicated the presence of room temperature magnetoelectric coupling behavior. Using high-frequency capacitance–voltage measurements, the fixed oxide charge density, interface trap density and dielectric constant were estimated on Au/BDFO/Si capacitors. These results suggest the integrated circuit compatible application potential of BDFO films in the field of micro-electro-mechanical systems and non-volatile memories.

Electrical properties changes induced by electron radiation at TiO2/Si interface

TiO2/Si structures were fabricated by electron beam evaporation, and exposed to electron beam irradiation to investigate their electrical properties using the high frequency capacitance–voltage measurements. It was found that samples annealed in oxygen became more radiation resistant than un-annealed samples, which can be explained by the Ti valence variations induced by radiation. The samples were characterized by X-ray diffraction to show the Ti2O3 crystalline phase transformed to anatase-crystalline phase after oxygen annealing.

Nonvolatile Memory Effects of NiO Layers Embedded in Al[sub 2]O[sub 3] High-k Dielectrics Using Atomic Layer Deposition

Nonvolatile memory effects of Al 2 O 3 /NiO/Al 2 O 3 nanolaminates deposited through atomic layer deposition were investigated. The memory structure was constructed without interruption in the order of Al 2 O 3 /NiO/Al 2 O 3 thin-film deposition on Si wafers. The memory characteristics were analyzed through high frequency capacitance―voltage measurement along with high resolution images of the aforementioned nanolaminates. The defective nature of nickel oxide produces a significantly large memory window; the largest memory window observed was 13.8 V. The peculiar memory characteristics were understood in terms of the constituent tunnel and charge-trapping layers in the metal gate/high-k oxide/semiconducting oxide/high-k oxide/Si memory structures.

Effect of Postoxidation Annealing on High Temperature Grown SiO2 / 4H-SiC Interfaces

was grown by dry thermal oxidation (at 1175, 1300, or ) on n-type 4H-SiC substrates. The samples were prepared by subsequently exposing the grown film on 4H-SiC to postoxidation annealing (POA) treatment using nitric oxide (NO) gas. The interfaces were characterized by high frequency capacitance–voltage measurements, X-ray photoelectron spectroscopy (XPS), and ellipsometry. The interface trap density of the dry oxide grown at was much lower than others. At a higher grown temperature , the electrical and physical properties of the oxide were not improved compared to those oxides grown at . The XPS measurements provided evidence for the presence of intermediate oxidation states of Si oxycarbide in all samples. The areal densities of the intermediate oxidation states affected the interface trap density. The NO POA treatment significantly improved the interface trap density, the near-interface trap density, and the effective oxide charge density of the oxides grown at 1175 and . But, this improvement was not observed for the oxide grown at . The electrical properties of the metal-oxide-semiconductor devices fabricated using these oxides have also been discussed in terms of the oxide chemical compositions, which were determined by XPS and an oxide etching test.

Physical and optoelectronic characterization of reactively sputtered molybdenum-silicon-nitride alloy metal gate electrodes

With continued transistor scaling, work function tuning of metal gates has become important for advanced complementary-metal-oxide-silicon applications. The work function tuning of reactively sputtered MoxSiyNz (also referred to as MoSiN) gates has been studied through the incorporation of nitrogen. The nitrogen concentration in the MoSiN films was altered by controlling the gas flow ratio, RN=N2/(N2+Ar), during gate deposition. The sheet resistance (Rs) of blanket MoSiN films, measured using four-point resistance method, was found to increase as the gas flow ratio was varied from 10% to 40%. Current-voltage measurements confirmed excellent electrical stability of MoSiN/SiO2/p-Si gate stack for applied electric fields ranging up to 6 MV/cm. High frequency capacitance-voltage measurements were used to extract the MoSiN work function (Φm) using the relationship between the flatband voltage (VFB) and the oxide thickness (tox). The extracted MoSiN/SiO2 interfacial barrier heights, obtained through the internal photoemission of electrons, were used to corroborate the extracted values of MoSiN work function. The MoSiN work functions (Φm), extracted independently using both techniques, were consistent and were observed to decrease with increasing gas flow ratio [N2/(N2+Ar)]. Secondary ion mass spectrometry depth analysis revealed uniform distribution of nitrogen throughout the bulk MoSiN films, with no piling up at gate-dielectric interface. X-ray photoelectron spectroscopy surface analysis suggested a steady increase in the Mo–N bonds, and therefore the total nitrogen concentration (from ∼20% to 32%), as the gas flow ratio is increased from 10% to 40%. A similar trend was observed in the nitrogen concentration (in percent), measured using Rutherford backscattering spectroscopy, for these gate deposition conditions. These material characterization results demonstrate that the increase in nitrogen concentration in MoSiN films is consistent with the lowering of MoSiN work function. Moreover, the work function of reactively sputtered MoxSiyNz films was found to be variable over ∼0.3 eV by adjusting the nitrogen concentration.

Memory properties of oxide–nitride–oxynitride stack structure using ultra-thin oxynitrided film as tunneling layer for nonvolatile memory device on glass

In this work, metal–oxide–nitride–oxynitride–silicon (MONOS) devices with silicon oxynitride film as tunneling layer of nonvolatile memory have been fabricated. General chemical vapor deposition cannot generate uniform thickness of ultra-thin tunneling layer for fabrication of the nonvolatile memory device on glass because of rough poly-silicon surface due to melting/crystallization of substrate during irradiation of laser beam. plasma-assisted oxynitridation is applied to form uniform and ultra-thin tunneling layer instead of conventional deposition and nonvolatile memory devices were fabricated with oxide–nitride–oxynitride stack structure. The charge storage effect of MONOS devices with different oxide–nitride–oxynitride thickness was investigated by high frequency capacitance–voltage measurement. The results demonstrate that the MONOS device using oxide–nitride–oxynitride stack structure with a ultra-thin tunneling oxynitride of 2.3 nm thickness, a charge trapping layer of silicon nitride of 10 nm thickness, and a blocking layer of 8.5 nm thickness have the relative large Δ V FB of 9.13 V in the large range voltage sweeps ranging from the large range capacitance–voltage characteristic curves. The difference of flatband voltage between the programming and erasing states was initially 4.92 V and decreased to 3.22 V after 1000 s.