High Floating Point Performance Research Articles

A Heterogeneous Parallel Algorithm for Euler-Lagrange Simulations of Liquid in Supersonic Flow

In spite of its prevalent usage for simulating the full-field process of the two-phase flow, the Euler–Lagrange method suffers from a heavy computing burden. Graphics processing units (GPUs), with their massively parallel architecture and high floating-point performance, provide new possibilities for high-efficiency simulation of liquid-jet-related systems. In this paper, a central processing unit/graphics processing unit (CPU/GPU) parallel algorithm based on the Euler–Lagrange scheme is established, in which both the gas and liquid phase are executed on the GPUs. To realize parallel tracking of the Lagrange droplets, a droplet dynamic management method is proposed, and a droplet-locating method is developed to address the cell. Liquid-jet-related simulations are performed on one core of the CPU with a GPU. The numerical results are consistent with the experiment. Compared with a setup using 32 cores of CPUs, considerable speedup is obtained, which is as high as 32.7 though it decreases to 20.2 with increasing droplets.

Correlation acceleration in GNSS software receivers using a CUDA-enabled GPU

The correlation process in a GNSS receiver tracking module can be computationally prohibitive if it is executed on a central processing unit (CPU) using single-instruction single-data algorithms. An efficient replacement for a CPU is a graphics processing unit (GPU). A GPU is composed of massive parallel processors with high floating point performance and memory bandwidth. It can be used to accelerate the burdensome correlation process in GNSS software receivers. We propose a novel GPU-based correlator architecture for GNSS software receivers, which is independent of the GPU device, the number of the processing channels, the signal type, and the correlation time. The proposed architecture is implemented and optimized using CUDA, a parallel computing platform and programming model for GPUs. We focus on the following aspects: the design and the time complexity analysis of the proposed GPU-based correlator algorithm, the tests that verify the correctness and the optimization of the implementation, and the performance evaluation of the optimized GPU-based correlator. Moreover, we introduce some new CUDA features that can be applied in a GPU-based correlator.

Performance modeling and analysis of heterogeneous lattice Boltzmann simulations on CPU–GPU clusters

Abstract Computational fluid dynamic simulations are in general very compute intensive. Only by parallel simulations on modern supercomputers the computational demands of complex simulation tasks can be satisfied. Facing these computational demands GPUs offer high performance, as they provide the high floating point performance and memory to processor chip bandwidth. To successfully utilize GPU clusters for the daily business of a large community, usable software frameworks must be established on these clusters. The development of such software frameworks is only feasible with maintainable software designs that consider performance as a design objective right from the start. For this work we extend the software design concepts to achieve more efficient and highly scalable multi-GPU parallelization within our software framework waLBerla for multi-physics simulations centered around the lattice Boltzmann method. Our software designs now also support a pure-MPI and a hybrid parallelization approach capable of heterogeneous simulations using CPUs and GPUs in parallel. For the first time weak and strong scaling performance results obtained on the Tsubame 2.0 cluster for more than 1000 GPUs are presented using waLBerla. With the help of a new communication model the parallel efficiency of our implementation is investigated and analyzed in a detailed and structured performance analysis. The suitability of the waLBerla framework for production runs on large GPU clusters is demonstrated. As one possible application we show results of strong scaling experiments for flows through a porous medium.

Memory Efficient Two-Pass 3D FFT Algorithm for Intel® Xeon PhiTM Coprocessor

Equipped with 512-bit wide SIMD instructions and large numbers of computing cores, the emerging x86-based Intel® Many Integrated Core (MIC) Architecture provides not only high floating-point performance, but also substantial off-chip memory bandwidth. The 3D FFT (three-dimensional fast Fourier transform) is a widely-studied algorithm; however, the conventional algorithm needs to traverse the data array three times. In each pass, it computes multiple 1D FFTs along one of three dimensions, giving rise to plenty of non-unit strided memory accesses. In this paper, we propose a two-pass 3D FFT algorithm, which mainly aims to reduce the amount of explicit data transfer between the memory and the on-chip cache. The main idea is to split one dimension into two sub-dimensions, and then combine the transform along each sub-dimension with one of the rest dimensions respectively. The difference in amount of TLB misses resulting from decomposition along different dimensions is analyzed in detail. Multi-level parallelism is leveraged on the many-core system for a high degree of parallelism and better data reuse of local cache. On top of this, a number of optimization techniques, such as memory padding, loop transformation and vectorization, are employed in our implementation to further enhance the performance. We evaluate the algorithm on the Intel® Xeon PhiTM coprocessor 7110P, and achieve a maximum performance of 136 Gflops with 240 threads in offload mode, which beats the vendor-specific Intel® MKL library by a factor of up to 2.22X.

Discrete particle simulation of gas–solid two-phase flows with multi-scale CPU–GPU hybrid computation

Though discrete particle simulation (DPS) has been widely used for investigating gas–solid flows from a more detailed level as compared to traditional two-fluid models (TFMs), it is still seriously limited by the computational cost when large scale systems are simulated. GPUs (graphic processing units), with their massive parallel architecture and high floating point performance, provide new possibilities for large-scale DPS. In this paper, a multi-scale CPU (central processing unit)–GPU hybrid computation mode is developed, in which the fluid flow is computed by CPU(s) while the particle motion is computed by GPU(s). To explore its feasibility, this mode is adopted to simulate the flow structures in the fluidization of Geldart D and A particles, respectively. Further coupled with an EMMS (energy minimization multi-scale) based meso-scale model, the flow behavior in an industrial fluidized bed is finally simulated, shedding light on the engineering applications of DPS, as an alternative to TFM.

Sparse matrix solvers on the GPU

Many computer graphics applications require high-intensity numerical simulation. We show that such computations can be performed efficiently on the GPU, which we regard as a full function streaming processor with high floating-point performance. We implemented two basic, broadly useful, computational kernels: a sparse matrix conjugate gradient solver and a regular-grid multigrid solver . Real time applications ranging from mesh smoothing and parameterization to fluid solvers and solid mechanics can greatly benefit from these, evidence our example applications of geometric flow and fluid simulation running on NVIDIA's GeForce FX.

Data-parallel total variation diminishing method for sonic boom calculations

Sonic boom predictions are shown for the near and midfield and comparisons are made with experimental data. The computations are performed on the Thinking Machines' CM-5 massively parallel supercomputer to utilize its large available memory and high floating point performance. A second-order-accurate total variation diminishing scheme is used to solve the Euler equations in the computations. Additionally, a recently developed implicit method, based on the LU-SGS algorithm, is used to speed the convergence and accuracy of the steady- state computations. The method is shown to work well on near- and midfield sonic boom predictions for several test cases. HE projected use of the high speed civil transport (HSCT) has drawn attention to the problems associated with the noise due to sonic booms.1 An accurate and efficient sonic boom prediction methodology is needed for the assessment of various proposed HSCT configurations. One such method that utilizes the power of massively parallel supercomputers is presented here. A review of current sonic boom prediction methods is given by Plotkin.2 Many of these methods are based on the modified linear analysis of Whitham 3 and Walkden.4 Other methods have been developed based on a modified method of char- acteristics that approximately account for the effects of three- dimensional flows. Experimental and analytical studies have shown that these methods lose effectiveness as freestream Mach number approaches 3. In high Mach number regions there are strong shock waves with significant entropy gen- eration. The linear-based methods neglect these production terms.5 A modified method of characteristi cs has been de- veloped that can account for these terms,6 but it requires nonlinear near-field initial data that is difficult to obtain com- putationally or experimentall y. Several authors have developed prediction methods based on near-field solutions of the Euler or Navier-Stokes equa- tions.7-8 Most of these methods involve marching in one spatial dimension with an implicit Euler scheme or a parabolized Navier-Stokes (PNS) algorithm. These solutions are used in conjuction with Whitham's F-function to evaluate the far-field pressure signature. The existing prediction methods are un- attractive for several reasons. First, additional accuracy in the marching direction greatly increases the computational time. Also, they do not employ methods designed to resolve shock waves effectively. Finally, they are not easily implemented on massively parallel supercomputers. Accurate shock resolution is needed in the computational fluid dynamic (CFD) methods to determine the far-field pres- sure signature effectively. Since the prediction methods are dependent on shock resolution it is desirable to use a com- putational method that is designed to capture shock waves. The total variation diminishing (TVD) schemes developed by Harten,9 Yee,10 and others are well suited for this purpose. In this study a second-order-accurate TVD scheme is used to determine the pressure field about several models. These so- lutions are then compared with experiment.

Machine organization of the IBM RISC System/6000 processor

The IBM RISC System/6000* processor is a second-generation RISC processor which reduces the execution pipeline penalties caused by branch instructions and also provides high floating-point performance. It employs multiple functional units which operate concurrently to maximize the instruction execution rate. By employing these advanced machine-organization techniques, it can execute up to four instructions simultaneously. Approximately 11 MFLOPS are achieved on the LINPACK benchmarks.

A pipelined interface for high floating-point performance with precise exceptions

Two options are presented that were considered for a pipelined interface between a central processing unit (CPU) and a floating-point coprocessor (FPU), along with the CPU recovery mechanisms that provide precise floating-point exceptions for each option. The first option supports parallel execution of both floating-point and integer instructions, while the second option pipelines only the execution of floating-point instructions. The use of the second option in National Semiconductor's 32532/32580 processor cluster because it offers high performance with significantly lower complexity. The 32532 microprocessor features a pipelined slave protocol that hides the CPU-FPU communication overhead for most floating-point instructions by pipelining their execution. A simple recovery mechanism implemented within the CPU maintains the precision of floating-point exceptions. As a result, the 32532 microprocessor supports very high floating point performance without sacrificing software compatibility with previous Series 32000 CPU-FPU clusters.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>