High-end FPGA Research Articles

A multipurpose test and measurement module with touchscreen and computer interface for engineering and technical education

ABSTRACTTest and measurement devices (TMD) are the core tools for the engineering and technical education on the field of electrical and electronics. This study is mainly concentrated on the development of a low cost, multifunction original equipment manufacturer (OEM) product intended to be used in conventional TMD free educational training sets. An enhancement on the interactive learning is also demonstrated as a consequence of embedding computer interfaced TMD to the conventional sets. While the technical requirements for such an embedded system can be achieved by the use of high end microprocessors or FPGAs, this study is aimed to develop a cost effective solution with the low end microcontrollers which is only available with hardware and firmware optimization during the design cycle. © 2016 Wiley Periodicals, Inc. Comput Appl Eng Educ 24:905–913, 2016; View this article online at wileyonlinelibrary.com/journal/cae; DOI 10.1002/cae.21760

Cost Breakdown of 2.5D and 3D Packaging

2.5D and 3D packaging can provide significant size and performance advantages over other packaging technologies. However, these advantages usually come at a high price. Since 2.5D and 3D packaging costs are significant, today they are only used if no other option can meet the product requirements, and most of these applications are relatively low volume. Products such as high end FPGAs, high performance GPUs, and high bandwidth memory are great applications but none have volume requirements close to mobile phones or tablets. Without the benefit of volume production, the cost of 2.5D and 3D packaging could stay high for a long time. In this paper, we will provide cost model results of a complete 2.5D and 3D manufacturing process. Each manufacturing activity will be included and the key cost drivers will be analyzed regarding future cost reductions. Expensive activities that are well down the learning curve (RDL creation, CMP, etc.) will probably not change much in the future. However, expensive activities that are new to this process (DRIE, temporary bond/debond, etc.) provide good opportunities for cost reduction. A variety of scenarios will be included to understand how design characteristics impact the cost. Understanding how and why the dominant cost components will change over time is critical to accurately predicting the future cost of 2.5D and 3D packaging.

A neuromorphic implementation of multiple spike-timing synaptic plasticity rules for large-scale neural networks.

We present a neuromorphic implementation of multiple synaptic plasticity learning rules, which include both Spike Timing Dependent Plasticity (STDP) and Spike Timing Dependent Delay Plasticity (STDDP). We present a fully digital implementation as well as a mixed-signal implementation, both of which use a novel dynamic-assignment time-multiplexing approach and support up to 226 (64M) synaptic plasticity elements. Rather than implementing dedicated synapses for particular types of synaptic plasticity, we implemented a more generic synaptic plasticity adaptor array that is separate from the neurons in the neural network. Each adaptor performs synaptic plasticity according to the arrival times of the pre- and post-synaptic spikes assigned to it, and sends out a weighted or delayed pre-synaptic spike to the post-synaptic neuron in the neural network. This strategy provides great flexibility for building complex large-scale neural networks, as a neural network can be configured for multiple synaptic plasticity rules without changing its structure. We validate the proposed neuromorphic implementations with measurement results and illustrate that the circuits are capable of performing both STDP and STDDP. We argue that it is practical to scale the work presented here up to 236 (64G) synaptic adaptors on a current high-end FPGA platform.

Architecture of a Fully Pipelined Real-Time Cellular Neural Network Emulator

In this paper, architecture of a Real-Time Cellular Neural Network (CNN) Processor (RTCNNP-v2) is given and the implementation results are discussed. The proposed architecture has a fully pipelined structure, capable of processing full-HD 1080p@60 (1920 × 1080 resolution at 60 Hz frame rate, 124.4 MHz visible pixel rate) video streams, which is implemented on both high-end and low-cost FPGA devices, Altera Stratix IV GX 230, and Cyclone III C 25, respectively. Many features of the architecture are designed to be either pre-synthesis configurable or runtime programmable, which makes the processor extremely flexible, reusable, scalable, and practical.

UWB microwave imaging for breast cancer detection

An UWB microwave imaging system for breast cancer detection consists of antennas, transceivers, and a high-performance embedded system for elaborating the received signals and reconstructing breast images. In this article we focus on this embedded system. To accelerate the image reconstruction, the Beamforming phase has to be implemented in a parallel fashion. We assess its implementation in three currently available high-end platforms based on a multicore CPU, a GPU, and an FPGA, respectively. We then project the results applying technology scaling rules to future many-core CPUs, many-thread GPUs, and advanced FPGAs. We consider an optimistic case in which available resources increase according to Moore's law only, and a pessimistic case in which only a fraction of those resources are available due to a limited power budget. In both scenarios, an implementation that includes a high-end FPGA outperforms the other alternatives. Since the number of effectively usable cores in future many-cores will be power-limited, and there is a trend toward the integration of power-efficient accelerators, we conjecture that a chip consisting of a many-core section and a reconfigurable logic section will be the perfect platform for this application.

And then there were none

Programmers are turning to radical architectures such as reconfigurable hardware (FPGAs) to achieve performance. But such systems, programmed at a very low level in languages with impoverished abstractions, are orders of magnitude more complex to use than conventional CPUs. The continued exponential increase in transistors, combined with the desire to implement ever more sophisticated algorithms, makes it imperative that such systems be programmed at much higher levels of abstraction. One of the fundamental high-level language features is automatic memory management in the form of garbage collection.We present the first implementation of a complete garbage collector in hardware (as opposed to previous hardware-assist techniques), using an FPGA and its on-chip memory. Using a completely concurrent snapshot algorithm, it provides single-cycle access to the heap, and never stalls the mutator for even a single cycle, achieving a deterministic mutator utilization (MMU) of 100%.We have synthesized the collector to hardware and show that it never consumes more than 1% of the logic resources of a high-end FPGA. For comparison we also implemented explicit (malloc/free) memory management, and show that real-time collection is about 4% to 17% slower than malloc, with comparable energy consumption. Surprisingly, in hardware real-time collection is superior to stop-the-world collection on every performance axis, and even for stressful micro-benchmarks can achieve 100% MMU with heaps as small as 1.01 to 1.4 times the absolute minimum.

Multicasting Mesh AER: A Scalable Assembly Approach for Reconfigurable Neuromorphic Structured AER Systems. Application to ConvNets

This paper presents a modular, scalable approach to assembling hierarchically structured neuromorphic Address Event Representation (AER) systems. The method consists of arranging modules in a 2D mesh, each communicating bidirectionally with all four neighbors. Address events include a module label. Each module includes an AER router which decides how to route address events. Two routing approaches have been proposed, analyzed and tested, using either destination or source module labels. Our analyses reveal that depending on traffic conditions and network topologies either one or the other approach may result in better performance. Experimental results are given after testing the approach using high-end Virtex-6 FPGAs. The approach is proposed for both single and multiple FPGAs, in which case a special bidirectional parallel-serial AER link with flow control is exploited, using the FPGA Rocket-I/O interfaces. Extensive test results are provided exploiting convolution modules of 64 × 64 pixels with kernels with sizes up to 11 × 11, which process real sensory data from a Dynamic Vision Sensor (DVS) retina. One single Virtex-6 FPGA can hold up to 64 of these convolution modules, which is equivalent to a neural network with 262 × 10(3) neurons and almost 32 million synapses.

Partial bitstream protection for low-cost FPGAs with physical unclonable function, obfuscation, and dynamic partial self reconfiguration

This paper proposes a technique based on Physical Unclonable Functions (PUFs), obfuscation, and Dynamic Partial Self Reconfiguration (DPSR) to protect partial FPGA configuration bitstreams from cloning and reverse engineering. With the aid of this technique, we are able to do the equivalent of partial bitstream encryption on low-cost FPGAs, which is only featured on high-end FPGAs. Low-cost FPGAs do not even have built-in support for encrypted (full) bitstreams. Through DPSR, our PUF implementation does not steal real estate from the encrypted design. We also present a new DPSR flow for Xilinx FPGAs, which is difference-based but still allows modular design. It works regardless of the amount of difference between Partial Reconfiguration (PR) modules and is called DPSR-LD, where LD stands for Large-Difference. DPSR-LD is an enabler especially for Spartan-6 FPGA family, as Xilinx currently supports PR on Spartan-6 only through the difference-based flow and only for small differences. Our DPSR-LD also includes a controller that interfaces to the ICAP and can process compressed bitstreams. It is called ICAP+ and occupies only 1% of Spartan-6 slices.

Real-time background generation and foreground object segmentation for high-definition colour video stream in FPGA device

The processing of a high-definition video stream in real-time is a challenging task for embedded systems. However, modern FPGA devices have both a high operating frequency and sufficient logic resources to be successfully used in these tasks. In this article, an advanced system that is able to generate and maintain a complex background model for a scene as well as segment the foreground for an HD colour video stream (1,920 × 1,080 @ 60 fps) in real-time is presented. The possible application ranges from video surveillance to machine vision systems. That is, in all cases, when information is needed about which objects are new or moving in the scene. Excellent results are obtained by using the CIE Lab colour space, advanced background representation as well as integrating information about lightness, colour and texture in the segmentation step. Finally, the complete system is implemented in a single high-end FPGA device.

A fully automated reconfigurable calculation engine dedicated to the real-time simulation of high switching frequency power electronic circuits

Real-time simulation allows rapid deployment and thorough testing of prototyped hardware in the automotive and aerospace industries. However, the simulation of power electronic circuits (PECs) in the context of PC-based simulations is challenging for several reasons, and imposes a limit in the 1–5kHz range to the achievable switching frequencies. As FPGA devices gain computing power, conducting the real-time simulation of PECs on chip becomes an attractive alternative. This paper demonstrates the feasibility of high-performance floating-point calculation engines aimed for the real-time simulation of PECs on high-end and low-cost FPGAs as well. The paper discusses emerging paradigms for reconfigurable floating-point computing that favor optimal performance and offer near double precision arithmetic at a minimal hardware cost. The effectiveness of the approach is demonstrated by considering three different circuit topologies and simulating their high-frequency stimulation (20kHz) using the same automated calculation engine. The considered circuits are a boost converter, a two-level three-phase bridge, and a two-level-three-phase bridge driven by a boost converter.

And then there were none

Programmers are turning to radical architectures such as reconfigurable hardware (FPGAs) to achieve performance. But such systems, programmed at a very low level in languages with impoverished abstractions, are orders of magnitude more complex to use than conventional CPUs. The continued exponential increase in transistors, combined with the desire to implement ever more sophisticated algorithms, makes it imperative that such systems be programmed at much higher levels of abstraction. One of the fundamental high-level language features is automatic memory management in the form of garbage collection. We present the first implementation of a complete garbage collector in hardware (as opposed to previous "hardware-assist" techniques), using an FPGA and its on-chip memory. Using a completely concurrent snapshot algorithm, it provides single-cycle access to the heap, and never stalls the mutator for even a single cycle, achieving a deterministic mutator utilization (MMU) of 100%. We have synthesized the collector to hardware and show that it never consumes more than 1% of the logic resources of a high-end FPGA. For comparison we also implemented explicit (malloc/free) memory management, and show that real-time collection is about 4% to 17% slower than malloc, with comparable energy consumption. Surprisingly, in hardware real-time collection is superior to stop-the-world collection on every performance axis, and even for stressful micro-benchmarks can achieve 100% MMU with heaps as small as 1.01 to 1.4 times the absolute minimum.

What is timing-closure in high-end FPGAs?

Timing-closure is a growing concern for FPGA designers, particularly with the recent introduction of multi-million gate architectures fabricated at the 90 nm and 65 nm technology nodes. It is not sufficient for a timing-closure solution - the entire flow, including synthesis - to meet only the required timing; such a solution must also minimize the number of time-consuming synthesis-place-route iterations and provide results that remain stable across multiple physical synthesis runs and during final routing.