High-end Field Programmable Gate Arrays Research Articles

X-ray Tomography Reconstruction Accelerated on FPGA through High-Level Synthesis Tools.

Model-Based Iterative Reconstruction (MBIR) algorithms iteratively use expensive computational operators of forward and backward projections. The irregular memory access pattern of these operators makes them a memory-bound application. Their computation time must be reduced to meet clinical routine constraints. This paper proposes a hardware accelerator architecture based on Field Programmable Gate Arrays (FPGAs) through high-level language, as an alternative to GPU architecture. This acceleration is based on an offline memory access analysis to address the main bottleneck of the algorithm and maximize the data reuse rate. The offline analysis allows for the tuning of the architecture parameters so that they converge to an optimal solution. Then, the Berkeley Roofline model guides our optimization steps by iteratively analyzing the design performance. Our design flow significantly improved the algorithm's computational intensity and overcame the memory bottleneck. Thus, our architecture takes advantage of the FPGA local memory to achieve significant memory bandwidth and efficiently harness the pipeline without stalling the computation. Furthermore, we present the scaling-up strategy from mid-range FPGA to high-end FPGA and any concerns of portability. We used two Intel FPGA devices to implement the algorithm, and then we compared the results with our GPU implementation in terms of speedup and energy efficiency. Our experimental results show that our design has achieved better computational throughput than the works on FPGA architectures reported in the literature.

Ultrafast ultrasound beamformer for plane wave imaging with field programmable gate array

In this work, we propose a novel method of implementing an ultrafast ultrasound beamformer for plane wave imaging (PWI) on a field programmable gate array (FPGA). First, a modified delay calculation method was proposed to (1) separate the transmit and receive delay, (2) reduce the size of delay profile, and (3) enable parallel beamforming by delay reuse and data vectorization. Second, a parallelized implementation of beamformer on single FPGA was proposed by (1) loading pre-calculated delay profile from external memory instead of calculating delay on run-time, (2) vectorizing channel data fetching, (3) compensating transmit and receive delays separately, and (4) using fixed summing networks to reduce consumption of logic resources. The proposed method was also highly scalable, which was demonstrated by implementing the beamformer with different beamforming rates ranging from 2.4 G to 9.6 G samples per second to three different sizes of FPGAs ranging from entry-level FPGA to high-end FPGA. The power consumption was less than 3 watts for 2.4 G samples per second beamforming rate, which demonstrates the possibility of implementing ultrafast ultrasound imaging on handheld probe. The FPGA beamformer’s results were compared with Verasonics CPU beamformer’s result to verify that the image quality was not compromised for speed.

Real-Time Inference With 2D Convolutional Neural Networks on Field Programmable Gate Arrays for High-Rate Particle Imaging Detectors.

We present a custom implementation of a 2D Convolutional Neural Network (CNN) as a viable application for real-time data selection in high-resolution and high-rate particle imaging detectors, making use of hardware acceleration in high-end Field Programmable Gate Arrays (FPGAs). To meet FPGA resource constraints, a two-layer CNN is optimized for accuracy and latency with KerasTuner, and network quantization is further used to minimize the computing resource utilization of the network. We use “High Level Synthesis for Machine Learning” (hls4ml) tools to test CNN deployment on a Xilinx UltraScale+ FPGA, which is an FPGA technology proposed for use in the front-end readout system of the future Deep Underground Neutrino Experiment (DUNE) particle detector. We evaluate network accuracy and estimate latency and hardware resource usage, and comment on the feasibility of applying CNNs for real-time data selection within the currently planned DUNE data acquisition system. This represents the first-ever exploration of employing 2D CNNs on FPGAs for DUNE.

Performance analysis of a millimeter wave MIMO channel estimation method in an embedded multi-core processor

The emerging Multi-Processor System-on-Chip (MPSoC) technology, which combines heterogeneous computing with the high performance of field programmable gate arrays (FPGA), is a promising platform for a large number of applications, including wireless communications and vehicular technology. In this specific application context, when multiple-input multiple-output (MIMO) scenarios are considered, the system usually has to manage a large number of communication links among sensors and antennas involving different vehicles and users. Millimeter wave (mmWave) communications are one of the key technology enablers toward achieving high data rates in beyond 5G systems (B5G). Communication at these frequency bands usually involves the use of large antenna arrays, often requiring high computational resources. One of the candidate platforms able to manage a huge number of communications is the Xilinx Zynq UltraScale+ EG Heterogeneous MPSoC, which is composed of a dual-core Cortex-R5, a quad-core ARM Cortex-A53, a graphics processing unit (GPU) and a high-end FPGA. This work analyzes the computational performance that requires a recent mmWave MIMO channel estimation algorithm in a platform of this kind. As a first approach, we will focus our work on the performance that can be achieved via the quad-core ARM Cortex-A53. To this end, we will use the libraries for numerical algebra (BLAS and LAPACK). The results show that our reference implementation is able to manage a large MIMO communication system with 256 antennas without exhausting platform resources.

Power Estimation and Validation of Embedded Multiplier Based on ANN and Regression Technique

Nowadays, high-end Field-Programmable Gate Arrays (FPGAs) are capable of implementing relatively high-performance systems in the field of Digital Signal Processing (DSP). Due to the abundant application of multipliers, their implementation efficiency and performance have become a critical issue in designing the DSP systems. On the other hand, FPGAs consume a large amount of power due to their complex circuitry. So, the power estimation of FPGA implementations at an early design stage has become a critical design metric. Various models are available in the literature based on Look-up Tables (LUTs), but not much literature is available on speed-optimized multiplier design using DSP slices only. In this paper, an embedded multiplier (12.0 IP core) has been analyzed and customized for different Input/Output (I/O) configurations to estimate the power using Vivado Design Suite (2014.4) targeted to the Zynq-family FPGA device (Zynq evolution and development kit). The embedded multiplier IP has been optimized for performance using two different approaches, i.e., Mults (DSP)-based and LUTs-based. Post-synthesis attributes have been used for formulating the power estimation models based on Artificial Neural Network (ANN) and curve fitting and regression technique. The power values estimated from the proposed models have been authenticated with reference to those assessed from the commercial tool. Based on the results obtained, ANN-based model provides average errors of 0.73% and 0.88% for the LUTs and DSP-based designs, respectively. Whereas, the model based on curve fitting and regression technique provides average errors of 3.61% and 1.59% for the LUTs and DSP-based designs, respectively. The timing analysis has been done to get the design performance and time complexity of the proposed models. Area analysis of the design has also been performed in order to report the resource utilization.

FPGA IMPLEMENTATION OF CNN FOR DEFECT CLASSIFICATION ON CMP RING

Defect inspection is a crucial part of industrial manufacturing. However, it relies heavily on human effort on manual visual inspection. Various machine vision techniques have been introduced to replace human labour and to improve inspection quality and efficiency. The limitation of these techniques is that the algorithms need to be engineered again with each different use case. In this work, a Convolutional Neural Network (CNN) is used to classify the defects of the Chemical Mechanical Planarization (CMP) ring. The trained CNN model achieved an accuracy of 91% and the time taken for each inference process is around 1800 msec. To achieve computational efficiency, the CNN model is performed on the embedded device. The previous implementation of embedded CNN deploys OpenCL-based high-level synthesis accelerator on a high-end Field Programmable Gate Array (FPGA) board. In this work, the model inference is accelerated by PipeCNN FPGA implementation on Cyclone-VSE DE1-SoC, a low-end embedded FPGA board. Several configurations of hardware parameters are tested to search for the best setup of the FPGA resources. The hardware implementation has improved approximately seven times faster, as the inference time for each classification has improved from 1800 msec to 250 msec. However, the model implemented using the hardware is observed to produce lower inference accuracy as the accuracy drops from 91% to 81%.

Evaluating the computational performance of the Xilinx Ultrascale+ EG Heterogeneous MPSoC

The emergent technology of Multi-Processor System-on-Chip (MPSoC), which combines heterogeneous computing with the high performance of Field Programmable Gate Arrays (FPGAs) is a very interesting platform for a huge number of applications ranging from medical imaging and augmented reality to high-performance computing in space. In this paper, we focus on the Xilinx Zynq UltraScale+ EG Heterogeneous MPSoC, which is composed of four different processing elements (PE): a dual-core Cortex-R5, a quad-core ARM Cortex-A53, a graphics processing unit (GPU) and a high end FPGA. Proper use of the heterogeneity and the different levels of parallelism of this platform becomes a challenging task. This paper evaluates this platform and each of its PEs to carry out fundamental operations in terms of computational performance. To this end, we evaluate image-based applications and a matrix multiplication kernel. On former, the image-based applications leverage the heterogeneity of the MPSoc and strategically distributes its tasks among both kinds of CPU cores and the FPGA. On the latter, we analyze separately each PE using different matrix multiplication benchmarks in order to assess and compare their performance in terms of MFlops. This kind of operations are being carried out for example in a large number of space-related applications where the MPSoCs are currently gaining momentum. Results stand out the fact that different PEs can collaborate efficiently with the aim of accelerating the computational-demanding tasks of an application. Another important aspect to highlight is that leveraging the parallel OpenBLAS library we achieve up to 12 GFlops with the four Cortex-A53 cores of the platform, which is a considerable performance for this kind of devices.

Is OpenCL Driven Reconfigurable Hardware Suitable for Virtualising 5G Infrastructure?

The Open Computing Language (OpenCL) is increasingly adopted for programming processors with reconfigurable hardware acceleration. The 5G telecommunication infrastructure, imposing strong latency constraints on the managed communications, may benefit from OpenCL-designed accelerated processing. This paper presents the first study to evaluate OpenCL hardware acceleration in the context of a 5G base station physical layer. The implementation and optimization process to accelerate the Orthogonal Frequency Division Multiplexing (OFDM) part of the 5G downlink is conducted on a high-end Field Programmable Gate Array (FPGA). We show that the proposed OpenCL implementation complies with the 5G processing timing requirements since the computation time is consistent with the present 5G deployment. However, to be suitable for 5G, the OpenCL platform must improve the data latency transfer between hardware and software. Moreover, a further enhancement for the OpenCL implementation is to improve the code by means of OpenCL optimization techniques. In this way, the performance can be further improved with respect to optimized software on vectorized high-end processors.

Practical Implementation of Multichannel Filtered-x Least Mean Square Algorithm Based on the Multiple-Parallel-Branch With Folding Architecture for Large-Scale Active Noise Control

Multichannel active noise control (MCANC) is widely recognized as an effective and efficient solution for acoustic noise and vibration cancellation, such as in high-dimensional ventilation ducts, open windows, and mechanical structures. The feedforward multichannel filtered-x least mean square (FFMCFxLMS) algorithm is commonly used to dynamically adjust the transfer function of the multichannel controllers for different noise environments. The computational load incurred by the FFMCFxLMS algorithm, however, increases exponentially with increasing channel count, thus requiring high-end field-programmable gate array (FPGA) processors. Nevertheless, such processors still need specific configurations to cope with soaring computing loads as the channel count increases. To achieve a high-efficiency implementation of the FFMCFxLMS algorithm with floating-point arithmetic, a novel architecture based on multiple-parallel-branch with folding (MPBF) technique is proposed. This architecture parallelizes the branches and reuses the multiplier and adder in each folded branch so that the tradeoff between throughput and the usage of the hardware resources is balanced. The proposed architecture is validated in an experimental setup that implements the FFMCFxLMS algorithm for the MCANC system with 24 reference sensors, 24 secondary sources, and 24 error sensors, at a sampling and throughput rates of 25 kHz and 260 Mb/s, respectively.

Combining Multiple Optimized FPGA-based Pulsar Search Modules Using OpenCL

Field-Programmable Gate Arrays (FPGAs) are widely used in the central signal processing design of the Square Kilometer Array (SKA) as hardware accelerators. The frequency domain acceleration search (FDAS) module is an important part of the SKA1-MID pulsar search engine. To develop for a yet to be finalized hardware, for cross-discipline interoperability and to achieve fast prototyping, OpenCL as a high-level FPGA synthesis approaches employed to create the sub-modules of FDAS. The FT convolution and the harmonic-summing plus some other minor sub-modules are elements in the FDAS module that have been well-optimized separately before. In this paper, we explore the design space of combining well-optimized designs, dealing with the ensuing need to trade-off and compromise. Pipeline computing is employed to handle multiple input arrays at high speed. The hardware target is to employ multiple high-end FPGAs to process the combined FDAS module. The results show interesting consequences, where the best individual solutions are not necessarily the best solutions for the speed of a pipeline where FPGA resources and memory bandwidth need to be shared. By proposing multiple buffering techniques to the pipeline, the combined FDAS module can achieve up to 2[Formula: see text] speedup over implementations without pipeline computing. We perform an extensive experimental evaluation on multiple high-end FPGA cards hosted in a workstation and compare to a technology comparable mid-range GPU.

Parallel hardware for faster morphological analysis

Morphological analysis of Arabic language is computationally intensive, has numerous forms and rules, and intrinsically parallel. The investigation presented in this paper confirms that the effective development of parallel algorithms and the derivation of corresponding processors in hardware enable implementations with appealing performance characteristics. The presented developments of parallel hardware comprise the application of a variety of algorithm modelling techniques, strategies for concurrent processing, and the creation of pioneering hardware implementations that target modern programmable devices. The investigation includes the creation of a linguistic-based stemmer for Arabic verb root extraction with extended infix processing to attain high-levels of accuracy. The implementations comprise three versions, namely, software, non-pipelined processor, and pipelined processor with high throughput. The targeted systems are high-performance multi-core processors for software implementations and high-end Field Programmable Gate Array systems for hardware implementations. The investigation includes a thorough evaluation of the methodology, and performance and accuracy analyses of the developed software and hardware implementations. The developed processors achieved significant speedups over the software implementation. The developed stemmer for verb root extraction with infix processing attained accuracies of 87% and 90.7% for analyzing the texts of the Holy Quran and its Chapter 29 – Surat Al-Ankabut.

An analysis framework for hardware and software implementations with applications from cryptography

With the richness of present-day hardware architectures, tightening the synergy between hardware and software has attracted a great attention. The interest in unified approaches paved the way for newborn frameworks that target hardware and software co-design. This paper confirms that a unified statistical framework can successfully classify algorithms based on a combination of the heterogeneous characteristics of their hardware and software implementations. The proposed framework produces customizable indicators for any hybridization of processing systems and can be contextualized for any area of application. The framework is used to develop the Lightness Indicator System (LIS) as a case-study that targets a set of cryptographic algorithms that are known in the literature to be tiny and light. The LIS targets state-of-the-art multi-core processors and high-end Field Programmable Gate Arrays (FPGAs). The presented work includes a generic benchmark model that aids the clear presentation of the framework and extensive performance analysis and evaluation.

Real-time Speed Limit Traffic Sign Detection System for Robust Automotive Environments

This paper describes a hardware-oriented algorithm and its conceptual implementation in a real-time speed limit traffic sign detection system on an automotive-oriented field-programmable gate array (FPGA). It solves the training and color dependence problems found in other research, which saw reduced recognition accuracy under unlearned conditions when color has changed. The algorithm is applicable to various platforms, such as color or grayscale cameras, high-resolution (4K) or low-resolution (VGA) cameras, and high-end or low-end FPGAs. It is also robust under various conditions, such as daytime, night time, and on rainy nights, and is adaptable to various countries’ speed limit traffic sign systems. The speed limit traffic sign candidates on each grayscale video frame are detected through two simple computational stages using global luminosity and local pixel direction. Pipeline implementation using results-sharing on overlap, application of a RAM-based shift register, and optimization of scan window sizes results in a small but highperformance implementation. The proposed system matches the processing speed requirement for a 60 fps system. The speed limit traffic sign recognition system achieves better than 98% accuracy in detection and recognition, even under difficult conditions such as rainy nights, and is implementable on the low-end, low-cost Xilinx Zynq automotive Z7020 FPGA.

A Reconfigurable Fabric for Accelerating Large-Scale Datacenter Services

To advance datacenter capabilities beyond what commodity server designs can provide, the authors designed and built a composable, reconfigurable fabric to accelerate large-scale software services. Each instantiation of the fabric consists of a 6 x 8 2D torus of high-end field-programmable gate arrays (FPGAs) embedded into a half-rack of 48 servers. The authors deployed the reconfigurable fabric in a bed of 1,632 servers and FPGAs in a production datacenter and successfully used it to accelerate the ranking portion of the Bing Web search engine by nearly a factor of two.

High Performance Stereo System for Dense 3-D Reconstruction

3-D stereo reconstruction, a technique that estimates per-pixel depth in a scene, is still a challenging problem mainly due to some prohibitive factors that limit its performance and computational ability. The aim of this paper is to present a new hardware-efficient disparity map computation, which is based on disparity space image processing using discrete dynamic systems. The hardware architecture of the proposed system was implemented on a high-end field programmable gate array (FPGA) device, offering real-time 3-D reconstruction speeds using a hardware aware architecture based on parallelism and process pipelining. The proposed architecture fulfills the requirements of real-world applications regarding resource usage, frame rates, and disparity resolution, while its implementation on an Altera Stratix IV family FPGA device can extract disparity maps of up to \(\mathbf {1280 \times 1024}\) pixels with up to 128 disparity levels under real-time or near real-time conditions at a clock rate of 168 MHz. Qualitative and quantitative results also demonstrate its performance and improvement over previous hardware-related studies, making our approach a suitable candidate for applications in which timing and processing constraints are critical.

Analysis and comparison of Direct Digital Frequency Synthesizers implemented on FPGA

The Direct Digital Frequency Synthesizer (DDFS) is a critical component routinely implemented in communication or signal processing systems.The recent literature proposes various DDFS implementation techniques that, implemented by using state of the art Application Specific Integrated Circuits (ASIC) technologies, provide ever improving performances in terms of speed, power dissipation and silicon area occupation.The performance trend provided by the advanced designs that target ASIC technologies is not guaranteed to remain the same when the target technology is a commercially available Field Programmable Gate Array (FPGA) device.This paper presents the FPGA implementation of the best performing DDFS architectures proposed to date. DDFS performance trends are compared with the ASIC implementations. Further, the state of the art DDFS circuits are modified in order to better suit the FPGA technology and compared against the DDFS implementations obtained using Intellectual Properties (IPs) included in the design suites of the FPGA manufacturers. The comparison is conducted considering as implementation target various (both low end, middle range, and high end) FPGA devices produced by different vendors. Considered performance parameters are the maximum working frequency, the dynamic power dissipation, the logic resource occupation, and the precision of the DDFS measured in terms of Spurious Free Dynamic Range (SFDR).The analysis shows that when dealing with FPGA implementations, it is important that the implemented architectures adapt to the internal logic resources of the FPGA. For low SFDR values the best performing architectures are the straightforward ROM based ones that optimally fit in the very fast Block RAM of the FPGA. When the required SFDR increases more advanced architectures are required. The optimal architectures also depend on the design choice of privileging high working frequency or reduced power dissipation.

Session details: HEART 2012 workshop

It is a pleasure for us to hold the Third International Workshop on Highly-Efficient Accelerators and Reconfigurable Technologies (HEART) in Okinawa Japan. Supercomputing using cost-effective accelerators, such as high-end field-programmable gate arrays, general-purpose graphics processing units and other specialized architectures, has become a major theme in high-performance computing. The goal of this workshop is to establish a forum for reporting state-of-the-art research on high-performance computing with such cost-effective accelerators. The workshop was affiliated to the ACM International Conference on Supercomputing in 2010, and became an independent workshop in 2011. This year it is held on the next two days after IEICE technical meeting on reconfigurable systems sharing some events. The program of the 3 rd HEART Workshop includes 15 regular papers and 10 posters. They are selected from 35 submissions from 12 countries (China, France, Germany, Hong Kong, Iran, Japan, Singapore, Spain, Sweden, Taiwan, UK, and US). The selected presentations span a wide range of topics related to the aim of the workshop and the two invited keynote lectures focus on Cyber-physical MPSoC Systems and supercomputing with GPU. An invited industrial lecture is a shared event with the IEICE reconfigurable systems technical meeting. Also before the reception, the second FPGA design contest "Connect 6 Revenge" demonstrates real-time matches between FPGA connect6 players.

Synchronous FPGA-Based High-Resolution Implementations of Digital Pulse-Width Modulators

Advantages of digital control in power electronics have led to an increasing use of digital pulse-width modulators (DPWM). However, the clock frequency requirements may exceed the operational limits when the power converter switching frequency is increased, while using classical DPWM architectures. In this paper, we present two synchronous designs to increase the resolution of the DPWM implemented on field programmable gate arrays (FPGA). The proposed circuits are based on the on-chip digital clock manager block present in the low-cost Spartan-3 FPGA series and on the I/O delay element (IODELAYE1) available in the high-end Virtex-6 FPGA series. These solutions have been implemented, tested, and compared to verify the performance of these architectures.

Geometry Unit for Analysis of Warped Image Features on Programmable Chips

Among many constraints applicable for embedded visions systems in industrial applications, desired processing performance is a determining factor of system costs. For technically and economically successful solutions, it is essential to match algorithms and architecture. High-end field programmable gate arrays open the perspective to vision systems on a programmable chip, leading to reduced size and higher performance. The architecture proposed in our previous publications in 2004 and 2006 is based on reusable building blocks. This paper continues with a particular building block for backward warping and interpolation of arbitrary shaped image regions, which can be used for many image processing tasks, including image statistics, projections, and template matching. The architecture is discussed and a typical application for template matching is presented. The suggested unit serves as universal basis for high-level image processing implemented on programmable chips, which enables a new generation of integrated high performance embedded vision systems maintaining reasonable system costs due to design reuse of basic units.